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參數(shù)資料
| 型號(hào)： | A1400AMT3C |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1400 MHz, MICROPROCESSOR, CPGA453 |
| 封裝： | STAGGERED, CERAMIC, PGA-453 |
| 文件頁數(shù)： | 39/90頁 |
| 文件大?。?/td> | 1497K |
| 代理商： | A1400AMT3C |
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30
Electrical Data
Chapter 7
AMD Athlon Processor Model 4 Data Sheet
23792I—June 2001
Preliminary Information
7.11
AMD Athlon System Bus AC and DC Characteristics
Table 11 shows the DC characteristics of the AMD Athlon
system bus used by the AMD Athlon Processor Model 4.
Table 11. AMD Athlon System Bus DC Characteristics
Symbol
Parameter
Condition
Min
Max
Units Notes
VREF
DC Input Reference Voltage
(0.5*VCC_CORE)
–50
(0.5*VCC_CORE)
+50
mV
1
IVREF_LEAK_P VREF Tristate Leakage Pullup
VIN = VREF Nominal
–100
A
IVREF_LEAK_N VREF Tristate Leakage Pulldown VIN = VREF Nominal
+100
A
VIH
Input High Voltage
VREF + 200
VCC_CORE +
500
mV
VIL
Input Low Voltage
–500
VREF – 200
mV
VOH
Output High Voltage
IOUT = –200A
0.85*VCC_CORE
VCC_CORE+500
mV
2
VOL
Output Low Voltage
IOUT = 1 mA
–500
400
mV
2
ILEAK_P
Tristate Leakage Pullup
VIN = VSS (Ground)
–1mA
ILEAK_N
Tristate Leakage Pulldown
VIN = VCC_CORE
Nominal
+1
mA
CIN
Input Pin Capacitance
4
12
pF
3
Notes:
1. VREF is nominally set to 50% of VCC_CORE with actual values that are specific to motherboard design implementation. VREF must be
created with a sufficiently accurate DC source and a sufficiently quiet AC response to adhere to the ± 50 mV specification listed above.
3. The following processor inputs have twice the listed capacitance because they connect to two input pads— SYSCLK, and SYSCLK#.
SYSCLK connects to CLKIN/RSTCLK. SYSCLK# connects to CLKIN#/RSTCLK#. For more information, see Table 16 on page 48 .
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