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參數(shù)資料
| 型號： | A1400AMT3C |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1400 MHz, MICROPROCESSOR, CPGA453 |
| 封裝： | STAGGERED, CERAMIC, PGA-453 |
| 文件頁數(shù)： | 79/90頁 |
| 文件大?。?/td> | 1497K |
| 代理商： | A1400AMT3C |
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66
Pin Descriptions
Chapter 10
AMD Athlon Processor Model 4 Data Sheet
23792I—June 2001
Preliminary Information
For more information, see the AMD Athlon Processor-Based
Motherboard Design Guide, order# 24363.
PLL Bypass and Test
Pins
PLLTEST# (AC3), PLLBYPASS# (AJ25), PLLMON1 (AN13),
PLLMON 2
(A L13),
PLLBY PA S S CLK
( AN15) ,
an d
PL LB YPA SSCL K # (A L 15) are the P LL bypa ss and te st
interface. This interface is tied disabled on the motherboard.
All six pin signals are routed to the debug connector. All four
processor inputs (PLLTEST#, PLLBYPASS#, PLLMON1, and
PLLMON2) are tied to VCC_CORE with pullup resistors.
PWROK Pin
The PWROK input to the processor must not be asserted until
all voltage planes in the system are within specification and all
system clocks are running within specification.
Fo r m o r e i n f o rmat i o n, See “ Signal and Po w e r-U p
SADDIN[1:0]# and
SADDOUT[1:0]# Pins
Th e AMD A th lon P rocessor Model 4 does not support
SADDIN[1:0]# or SADDOUT[1:0]#. SADDIN[1]# is tied to VCC
with pullup resistors, if this bit is not supported by the
Northbridge (future models can support SADDIN[1]#).
SADDOUT[1:0]# are tied to VCC with pullup resistors if these
pins are supported by the Northbridge. For more information,
see the AM D A t h l o n and AMD D uron System Bu s
Specification, order# 21902.
Scan Pins
SCANSHIFTEN (Q5), SCANCLK1 (S1), SCANINTEVAL (S3),
and SCANCLK2 (S5) are the scan interface. This interface is
AMD internal and is tied disabled with pulldown resistors to
ground on the motherboard.
SCHECK[7:0]# Pin
For systems that do not support ECC, SCHECK[7:0]# should be
treated as NC pins.
SMI# Pin
SMI# is an input that causes the processor to enter the system
management mode.
STPCLK# Pin
STPCLK# is an input that causes the processor to enter a lower
power mode and issue a Stop Grant special cycle.
SYSCLK and SYSCLK#
Pins
SYSCLK and SYSCLK# are differential input clock signals
provided to the processor’s PLL from a system-clock generator.
See “CLKIN, RSTCLK (SYSCLK) Pins” on page 62 for more
information.
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