參數(shù)資料
型號: A1400AMT3C
廠商: ADVANCED MICRO DEVICES INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 1400 MHz, MICROPROCESSOR, CPGA453
封裝: STAGGERED, CERAMIC, PGA-453
文件頁數(shù): 8/90頁
文件大?。?/td> 1497K
代理商: A1400AMT3C
2
Overview
Chapter 1
AMD Athlon Processor Model 4 Data Sheet
23792I—June 2001
Preliminary Information
The AMD Athlon processor microarchitecture incorporates
enhanced 3DNow! technology, a high-performance cache
architecture, and both a 200-MHz, 1.6-Gigabyte per second
system bus, and a 266 MHz, 2.1-Gigabyte per second system bus.
The AMD Athlon system bus combines the latest technological
advances, such as point-to-point topology, source-synchronous
packet-based transfers, and low-voltage signaling, to provide
the most powerful, scalable bus available for any x86 processor.
In addi ti on , com bi ne d wi th th e AMD 76 0 ch i pset , t he
AMD Athlon system bus interfaces with double-data rate
(DDR) memory subsystems.
The AMD Athlon processor is binary-compatible with existing
x86 software and backwards compatible with applications
optimized for MMX and 3DNow! instructions. Using a data
format and single-instruction multiple-data (SIMD) operations
based on the MMX instruction model, the AMD Athlon
processor can produce as many as four, 32-bit, single-precision
floating-point results per clock cycle. The enhanced 3DNow!
technology implemented in the AMD Athlon processor includes
new integer multimedia instructions and software-directed
data movement instructions for optimizing such applications as
digital content creation and streaming video for the internet, as
we ll as new inst ruct ions fo r digit a l s ig n al proc ess i ng
(DSP)/communications applications.
1.1
AMD Athlon Processor Model 4 Microarchitecture Summary
The following features summarize the AMD Athlon processor
microarchitecture:
s
The industry’s first nine-issue, superpipelined, superscalar
x86 processor microarchitecture designed for high clock
frequencies
s
Multiple x86 instruction decoders
s
Three
out-of-order,
superscalar,
fully
pipelined
floating-point execution units, which execute all x87
(floating-point), MMX and 3DNow! instructions
s
Three out-of-order, superscalar, pipelined integer units
s
Three
out-of-order,
superscalar,
pipelined
address
calculation units
s
72-entry instruction control unit
s
Advanced dynamic branch prediction
s
Enhanced 3DNow! technology with new instructions to
enable improved integer math calculations for speech or
video encoding and improved data movement for internet
plug-ins and other streaming applications
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