Revision 13 2-41 2.5 V GTL+ Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides" />
參數(shù)資料
型號: A3PE-STARTER-KIT-2
廠商: Microsemi SoC
文件頁數(shù): 114/162頁
文件大小: 0K
描述: KIT EVAL FOR A3PE1500 PROASIC3
產(chǎn)品變化通告: Kit/Part Number Change 25/Jul/2012
標準包裝: 1
系列: ProASIC3
類型: FPGA
適用于相關(guān)產(chǎn)品: A3PE1500
所含物品: 板,電源,編程器
其它名稱: 1100-1144
A3PE-STARTER-KIT
ProASIC3E Flash Family FPGAs
Revision 13
2-41
2.5 V GTL+
Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential
amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V.
Timing Characteristics
Table 2-57 Minimum and Maximum DC Input and Output Levels
2.5 V GTL+
VIL
VIH
VOL
VOH IOL IOH
IOSL
IOSH
IIL IIH
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VmA mA
Max.
mA1
Max.
mA1
A2 A2
33 mA
–0.3 VREF – 0.1 VREF + 0.1
3.6
0.6
33 33
124
169
10 10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
Figure 2-15 AC Loading
Table 2-58 AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring
Point* (V)
VREF (typ.) (V)
VTT (typ.) (V)
CLOAD (pF)
VREF – 0.1
VREF + 0.1
1.0
1.5
10
Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.
Test Point
10 pF
25
GTL+
VTT
Table 2-59 2.5 V GTL+
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 2.3 V, VREF = 1.0 V
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
Std.
0.60
2.21
0.04
1.51
0.43
2.25
2.10
4.48
4.34
ns
–1
0.51
1.88
0.04
1.29
0.36
1.91
1.79
3.81
3.69
ns
–2
0.45
1.65
0.03
1.13
0.32
1.68
1.57
3.35
3.24
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
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