Revision 13 2-11 Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logi" />
參數(shù)資料
型號: A3PE-STARTER-KIT-2
廠商: Microsemi SoC
文件頁數(shù): 81/162頁
文件大小: 0K
描述: KIT EVAL FOR A3PE1500 PROASIC3
產(chǎn)品變化通告: Kit/Part Number Change 25/Jul/2012
標(biāo)準(zhǔn)包裝: 1
系列: ProASIC3
類型: FPGA
適用于相關(guān)產(chǎn)品: A3PE1500
所含物品: 板,電源,編程器
其它名稱: 1100-1144
A3PE-STARTER-KIT
ProASIC3E Flash Family FPGAs
Revision 13
2-11
Guidelines
Toggle Rate Definition
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the
toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are
some examples:
The average toggle rate of a shift register is 100% as all flip-flop outputs toggle at half of the clock
frequency.
The average toggle rate of an 8-bit counter is 25%:
– Bit 0 (LSB) = 100%
– Bit 1
= 50%
– Bit 2
= 25%
–…
– Bit 7 (MSB) = 0.78125%
– Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8
Enable Rate Definition
Output enable rate is the average percentage of time during which tristate outputs are enabled. When
nontristate output buffers are used, the enable rate should be 100%.
Table 2-11 Toggle Rate Guidelines Recommended for Power Calculation
Component
Definition
Guideline
1
Toggle rate of VersaTile outputs
10%
2
I/O buffer toggle rate
10%
Table 2-12 Enable Rate Guidelines Recommended for Power Calculation
Component
Definition
Guideline
1
I/O output buffer enable rate
100%
2
RAM enable rate for read operations
12.5%
3
RAM enable rate for write operations
12.5%
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