Revision 13 2-19 Table 2-17 Summary of I/O Timing Characteristics—Software Default Settings " />
參數(shù)資料
型號： A3PE-STARTER-KIT-2
廠商： Microsemi SoC
文件頁數(shù)： 90/162頁
文件大?。?/td> 0K
描述： KIT EVAL FOR A3PE1500 PROASIC3
產(chǎn)品變化通告： Kit/Part Number Change 25/Jul/2012
標準包裝： 1
系列： ProASIC3
類型： FPGA
適用于相關(guān)產(chǎn)品： A3PE1500
所含物品： 板，電源，編程器
其它名稱： 1100-1144
A3PE-STARTER-KIT
ProASIC3E Flash Family FPGAs
Revision 13
2-19
Table 2-17 Summary of I/O Timing Characteristics—Software Default Settings
–2 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V
I/O Standard
Drive
Strength
(mA)
Equivalent
Software
Default
Drive
Strength
Option)1
Slew
Rate
Cap
acitiv
eLo
ad
(pF
)
Extern
al
Resisto
r(
)
t DOU
T(ns)
t DP
(ns)
t DIN
(n
s)
t PY
(ns)
t PY
S
(ns)
t EOU
T
(ns)
t ZL
(ns)
t ZH
(ns)
t LZ
(ns)
t HZ
(ns)
t ZLS
(n
s)
t ZHS
(ns)
3.3 V LVTTL /
3.3 V LVCMOS
12
High 35
–
0.49 2.74 0.03 0.90 1.17 0.32 2.79 2.14 2.45 2.70 4.46 3.81
3.3 V LVCMOS
Wide Range2
100 A
12
High 35
–
0.49 4.24 0.03 1.36 1.78 0.32 4.24 3.25 3.78 4.17 6.77 5.79
2.5 V LVCMOS
12
High 35
–
0.49 2.80 0.03 1.13 1.24 0.32 2.85 2.61 2.51 2.61 4.52 4.28
1.8 V LVCMOS
12
High 35
–
0.49 2.83 0.03 1.08 1.42 0.32 2.89 2.31 2.79 3.16 4.56 3.98
1.5 V LVCMOS
12
High 35
–
0.49 3.30 0.03 1.27 1.60 0.32 3.36 2.70 2.96 3.27 5.03 4.37
3.3 V PCI
Per PCI
spec
–
High 10
25 3 0.49 2.09 0.03 0.78 1.17 0.32 2.13 1.49 2.45 2.70 3.80 3.16
3.3 V PCI-X
Per PCI-X
spec
–
High 10
253 0.49 2.09 0.03 0.78 1.17 0.32 2.13 1.49 2.45 2.70 3.80 3.16
3.3 V GTL
20 4
–
High 10
25 0.45 1.55 0.03 2.19 – 0.32 1.52 1.55 –
– 3.19 3.22
2.5 V GTL
20 4
–
High 10
25 0.45 1.59 0.03 1.83 – 0.32 1.61 1.59 –
– 3.28 3.26
3.3 V GTL+
35
–
High 10
25 0.45 1.53 0.03 1.19 – 0.32 1.56 1.53 –
– 3.23 3.20
2.5 V GTL+
33
–
High 10
25 0.45 1.65 0.03 1.13 – 0.32 1.68 1.57 –
– 3.35 3.24
HSTL (I)
8
–
High 20
50 0.49 2.37 0.03 1.59 – 0.32 2.42 2.35 –
– 4.09 4.02
HSTL (II)
15 4
–
High 20
25 0.49 2.26 0.03 1.59 – 0.32 2.30 2.03 –
– 3.97 3.70
SSTL2 (I)
15
–
High 30
50 0.49 1.59 0.03 1.00 – 0.32 1.62 1.38 –
– 3.29 3.05
SSTL2 (II)
18
–
High 30
25 0.49 1.62 0.03 1.00 – 0.32 1.65 1.32 –
– 3.32 2.99
SSTL3 (I)
14
–
High 30
50 0.49 1.72 0.03 0.93 – 0.32 1.75 1.37 –
– 3.42 3.04
SSTL3 (II)
21
–
High 30
25 0.49 1.54 0.03 0.93 – 0.32 1.57 1.25 –
– 3.24 2.92
LVDS/B-LVDS/
M-LVDS
24
–
High –
–
0.49 1.40 0.03 1.36 –
–
LVPECL
24
–
High –
–
0.49 1.36 0.03 1.22 –
–
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 A. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3V wide range as specified in the JESD8b specification.
3. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-11 on page 2-37 for
connectivity. This resistor is not required during normal operation.
4. Output drive strength is below JEDEC specification.
5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5..
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