Revision 13 2-13 Figure 2-3 Input Buffer Timing Model and Delays (example) (R) PAD Y GND (F) 50% (R) (F) (R) " />
參數資料
型號: A3PE-STARTER-KIT-2
廠商: Microsemi SoC
文件頁數: 83/162頁
文件大?。?/td> 0K
描述: KIT EVAL FOR A3PE1500 PROASIC3
產品變化通告: Kit/Part Number Change 25/Jul/2012
標準包裝: 1
系列: ProASIC3
類型: FPGA
適用于相關產品: A3PE1500
所含物品: 板,電源,編程器
其它名稱: 1100-1144
A3PE-STARTER-KIT
ProASIC3E Flash Family FPGAs
Revision 13
2-13
Figure 2-3 Input Buffer Timing Model and Delays (example)
(R)
PAD
Y
GND
(F)
50%
(R)
(F)
(R)
DIN
GND
(F)
50%
PAD
Y
D
CLK
Q
I/O Interface
DIN
To Array
tDIN
VCC
tPYS
tPY
tPYS
tPY
VCC
Vtrip
VIH
VIL
tPY = MAX(tPY(R), tPY(F))
tDIN = MAX(tDIN(R), tDIN(F))
tPY
tDIN
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