Revision 13 2-3 I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and Industrial)
參數(shù)資料
型號: A3PE-STARTER-KIT-2
廠商: Microsemi SoC
文件頁數(shù): 72/162頁
文件大?。?/td> 0K
描述: KIT EVAL FOR A3PE1500 PROASIC3
產(chǎn)品變化通告: Kit/Part Number Change 25/Jul/2012
標(biāo)準(zhǔn)包裝: 1
系列: ProASIC3
類型: FPGA
適用于相關(guān)產(chǎn)品: A3PE1500
所含物品: 板,電源,編程器
其它名稱: 1100-1144
A3PE-STARTER-KIT
ProASIC3E Flash Family FPGAs
Revision 13
2-3
I/O Power-Up and Supply Voltage Thresholds for Power-On Reset
(Commercial and Industrial)
Sophisticated power-up management circuitry is designed into every ProASIC3E device. These circuits
ensure easy transition from the powered-off state to the powered-up state of the device. The many
different supplies can power up in any sequence with minimized current spikes or surges. In addition, the
I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1
There are five regions to consider during power-up.
ProASIC3E I/Os are activated only if ALL of the following three conditions are met:
1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4).
2. VCCI > VCC – 0.75 V (typical)
3. Chip is in the operating mode.
VCCI Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.2 V
Ramping down: 0.5 V < trip_point_down < 1.1 V
VCC Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.1 V
Ramping down: 0.5 V < trip_point_down < 1 V
VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically
built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:
During programming, I/Os become tristated and weakly pulled up to VCCI.
JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O
behavior.
Table 2-4 Overshoot and Undershoot Limits 1
VCCI and VMV
Average VCCI–GND Overshoot or
Undershoot Duration
as a Percentage of Clock Cycle2
Maximum Overshoot/
Undershoot2
2.7 V or less
10%
1.4 V
5%
1.49 V
3 V
10%
1.1 V
5%
1.19 V
3.3 V
10%
0.79 V
5%
0.88 V
3.6 V
10%
0.45 V
5%
0.54 V
Notes:
1. Based on reliability requirements at 85°C.
2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the
maximum overshoot/undershoot has to be reduced by 0.15 V.
3. This table does not provide PCI overshoot/undershoot limits.
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