2-80 Revision 13 Figure 2-51 FIFO FULL Flag and AFULL Flag Assertion Figure 2-52 FIFO E" />
參數(shù)資料
型號: A3PE-STARTER-KIT-2
廠商: Microsemi SoC
文件頁數(shù): 157/162頁
文件大?。?/td> 0K
描述: KIT EVAL FOR A3PE1500 PROASIC3
產(chǎn)品變化通告: Kit/Part Number Change 25/Jul/2012
標準包裝: 1
系列: ProASIC3
類型: FPGA
適用于相關產(chǎn)品: A3PE1500
所含物品: 板,電源,編程器
其它名稱: 1100-1144
A3PE-STARTER-KIT
ProASIC3E DC and Switching Characteristics
2-80
Revision 13
Figure 2-51 FIFO FULL Flag and AFULL Flag Assertion
Figure 2-52 FIFO EMPTY Flag and AEMPTY Flag Deassertion
Figure 2-53 FIFO FULL Flag and AFULL Flag Deassertion
NO MATCH
Dist = AFF_TH
MATCH (FULL)
tCKAF
tWCKFF
tCYC
WCLK
FULL
AFULL
WA/RA
(Address Counter)
WCLK
WA/RA
(Address Counter)
MATCH
(EMPTY)
NO MATCH
Dist = AEF_TH + 1
NO MATCH
RCLK
EMPTY
1st Rising
Edge
After 1st
Write
2nd Rising
Edge
After 1st
Write
tRCKEF
tCKAF
AEMPTY
Dist = AFF_TH – 1
MATCH (FULL)
NO MATCH
tWCKF
tCKAF
1st Rising
Edge
After 1st
Read
1st Rising
Edge
After 2nd
Read
RCLK
WA/RA
(Address Counter)
WCLK
FULL
AFULL
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