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參數(shù)資料
| 型號(hào)： | A42MX16-2VQ100 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁(yè)數(shù)： | 111/120頁(yè) |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX16-2VQ100 |
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90
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.13.5.11
Timer2 Compare Register – T2COR
The Compare Registers contain a 16-bit value that is continuously compared with the counter
value (T2CNT). A counter match can be used to generate a Compare interrupt, a counter reset,
an output clock CLK
T2 or to generate a waveform with the modulator on the output pins (T2O1,
T2O2).
The Compare Registers is a 16-bit register. To ensure that both the high and low bytes are writ-
ten simultaneously when the CPU writes to these registers, the access is performed using an
8-bit temporary High Byte Register (TEMP). This temporary register is shared by all 16-bit regis-
3.13.5.12
Timer2 Interrupt Flag Register – T2IFR
Bits 7..6 - Res: Reserved Bits
These bits are reserved bits at the ATA6289 and will always read as zero.
Bit 5 - T2TCF: Timer2 SSI Transmit Complete Flag Bit
This flag bit is set when the entire frame in the SSI Shift Register has been shifted out and there
are no new data currently present in the transmit buffer (T2MDR). The T2TCF flag bit is auto-
matically cleared when a transmit complete interrupt is executed, or it can be cleared by writing
a one to its bit location. The T2TCF flag can generate a Transmit Complete interrupt (see
description of the T2TCIM bit in Section 3.13.5.13 “Timer2 Interrupt Mask Register – T2IMR” on
page 91).
Bit 4 - T2TXF: Timer2 SSI Transmit Flag Bit
The T2TXF flag indicates if the transmit buffer (T2MDR) is ready to receive new data. If T2TXF
is one, the buffer is empty, and therefore ready to be written. The T2TXF flag can generate a
Data Register Empty interrupt (see description of the T2TXIM bit in Section 3.13.5.13 “Timer2
T2TXF is set after a reset to indicate that the SSI Transmitter is ready.
Bit 3 - T2RXF: Timer2 SSI Receive Flag Bit
This flag bit is set when there are unread data in the receive buffer and cleared when the receive
buffer is empty (i.e., does not contain any unread data). If the Timer2 SSI is disabled (T2SSIE =
“0” in the T2MRB register), the receive buffer will be cleared and consequently the T2RXF bit will
become zero. The T2RXF flag can be used to generate a Receive Complete interrupt (see
description of the T2RXIM bit in Section 3.13.5.13 “Timer2 Interrupt Mask Register – T2IMR” on
page 91).
Bit
7654
3210
T2CORH [15..8]
T2CORH
T2CORL [7..0]
T2CORL
Read/Write
R/W
Initial Value
0000
Bit
76
543
210
-
T2TCF
T2TXF
T2RXF
T2ICF
T2COF
T2OFF
T2IFR
Read/Write
R
R/W
Initial Value
00
010
000
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX16-2VQ100A | 40MX and 42MX FPGA Families |
| A42MX16-2VQ100B | 40MX and 42MX FPGA Families |
| A42MX16-2VQ100ES | 40MX and 42MX FPGA Families |
| A42MX16-3PQ100B | 40MX and 42MX FPGA Families |
| A42MX16-3BG100 | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-2VQ100A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2VQ100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2VQ100ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2VQ100I | 功能描述:IC FPGA MX SGL CHIP 24K 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| A42MX16-2VQ100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
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