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參數(shù)資料
| 型號： | A42MX16-2VQ100 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 51/120頁 |
| 文件大小： | 854K |
| 代理商： | A42MX16-2VQ100 |
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36
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.7.7
System Clock Prescaler (CLK)
The Atmel
ATA6289 has a system clock prescaler (Figure 3-14 on page 38), and the system
clock can be divided by setting the CLKPR register, see Section 3.7.8.1 “Clock Prescaler Regis-
ter – CLPR” on page 37. This feature can be used to decrease the system clock frequency and
the power consumption when the requirement for processing power is low. The input clock (CL)
for the prescaler is selectable by the Clock Module Unit, and it will affect the clock frequency of
the CPU and all synchronous peripherals. CLK
I/O, CLKCPU, and CLKFlash are divided by a factor
as shown in Table 3-10 on page 37.
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occur in the clock system. It also ensures that no intermediate frequency is higher than
neither the clock frequency corresponding to the previous setting, nor the clock frequency corre-
sponding to the new setting. The ripple-counter that implements the prescaler runs at the
frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it
is not possible to determine the state of the prescaler - even if it were readable, and the exact
time it takes to switch from one clock division to the other cannot be exactly predicted. To avoid
unintentional changes of clock frequency, a special write procedure must be followed to change
the CLKPS[2..0] bits:
1.
Write the Clock Prescaler Change Enable (CLPCE) bit to one and all other bits in
CLKPR to zero.
2.
Within four cycles, write the desired value to CLKPS[2..0] while writing a zero to
CLPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is
not interrupted.
3.7.8
Timer Clock Prescaler (CLT)
The Atmel ATA6289 has a timer clock prescaler (Figure 3-14 on page 38), and the timer clock
can be divided by setting the CLKPR register, refer to Section 3.7.8.1 “Clock Prescaler Register
– CLPR” on page 37. This feature can be used to decrease the timer clock frequency. The input
clock (CL) for the prescaler is selectable by the Clock Module Unit, and it will affect the clock fre-
quency of the Timers are divided by a factor as shown in Table 3-9 on page 37. When switching
between prescaler settings, the Timer Clock Prescaler ensures that no glitches occur in the
clock system. It also ensures that no intermediate frequency is higher than neither the clock fre-
quency corresponding to the previous setting, nor the clock frequency corresponding to the new
setting. The ripple-counter that implements the prescaler runs at the frequency of the undivided
clock, which may be faster than the Timer's clock frequency. Hence, it is not possible to deter-
mine the state of the prescaler - even if it were readable, and the exact time it takes to switch
from one clock division to the other cannot be exactly predicted. To avoid unintentional changes
of clock frequency, a special write procedure must be followed to change the CLTPS[2..0] bits:
1.
Write the Clock Prescaler Change Enable (CLPCE) bit to one and all other bits in
CLKPR to zero.
2.
Within four cycles, write the desired value to CLTPS[2..0] while writing a zero to
CLPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is
not interrupted.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX16-2VQ100A | 40MX and 42MX FPGA Families |
| A42MX16-2VQ100B | 40MX and 42MX FPGA Families |
| A42MX16-2VQ100ES | 40MX and 42MX FPGA Families |
| A42MX16-3PQ100B | 40MX and 42MX FPGA Families |
| A42MX16-3BG100 | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-2VQ100A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2VQ100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2VQ100ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2VQ100I | 功能描述:IC FPGA MX SGL CHIP 24K 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| A42MX16-2VQ100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
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