參數(shù)資料
型號(hào)： A42MX16-2VQ100
廠商： Electronic Theatre Controls, Inc.
英文描述： 40MX and 42MX FPGA Families
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 93/120頁
文件大?。?/td> 854K
代理商： A42MX16-2VQ100
74
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
The Timer0 can also be used as a watchdog timer to prevent a system from stalling. The watch-
dog divider is a 3-bit counter that is supplied by a separate output clock (CLK
WD) of Timer0. It
generates a system reset when the 3-bit counter overflows. To avoid this, the 3-bit counter must
be reset before it overflows. The application software has to accomplish this by executing the
WDR
Watchdog Reset
instruction to restart the Watchdog Counter before the time-out value
is reached. The Watchdog Counter is also reset when it is disabled and when a Chip Reset
occurs. Eight different clock cycle periods can be selected to determine the reset period. If the
reset period expires without another Reset, the ATA6289 resets and executes from the reset
vector. By controlling the Watchdog Timer0 prescaler, the Watchdog Reset interval can be
adjusted as shown in Table 3-31 on page 77 via the WDPS[2..0] bits in the Timer0 watchdog
control register WDTCR.
To prevent unintentional disabling of the Watchdog or unintentional change of time-out period,
two different safety levels are selected by the fuse WDTON as shown in Table 3-30.
3.13.3.1
Watchdog Timer0 Control Register
Bits 7..5 - Res: Reserved Bits
These bits are reserved bits at the ATA6289 and will always read as zero.
Bit 4 - WDCE: WatchDog Change Enable Bit
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not
be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to
description of the WDE bit for a Watchdog disable procedure. This bit must also be set when
changing the watchdog prescaler bits, refer to Table 3-30
Bit 3 - WDE: WatchDog Enable Bit
When the WDE bit is written to logic one, the Watchdog Timer is enabled, and if the WDE bit is
written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the
WDCE bit has logic level one. To further ensure program security the Watchdog set-up must fol-
low a special timed sequence. To disable the Watchdog Timer by clearing the WDE bit following
procedure must be executed:
1.
In one operation, write a logic one to WDCE and WDE. A logic one must be written to
WDE even though it is set to one before the disable operation starts.
2.
Within the next four clock cycles, write logic 0 to WDE. The Watchdog will be disabled.
Table 3-30.
Configuration as a Function of the Fuse Settings of WDTON
WDTON
Safety Level WDT Initial State How to Disable the WDT How to Change Time-out
Unprogrammed
1
Disabled
Timed sequence
Programmed
2
Enabled
Always enabled
Timed sequence
Bit
76
543
210
-
WDCE
WDE
WDPS2
WDPS1
WDPS0 WDTCR
Read/Write
R
R/W
Initial Value
00
000
相關(guān)PDF資料
PDF描述
A42MX16-2VQ100A 40MX and 42MX FPGA Families
A42MX16-2VQ100B 40MX and 42MX FPGA Families
A42MX16-2VQ100ES 40MX and 42MX FPGA Families
A42MX16-3PQ100B 40MX and 42MX FPGA Families
A42MX16-3BG100 40MX and 42MX FPGA Families
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX16-2VQ100A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-2VQ100B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-2VQ100ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-2VQ100I 功能描述:IC FPGA MX SGL CHIP 24K 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
A42MX16-2VQ100M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
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