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參數(shù)資料
| 型號(hào)： | A42MX16-2VQ100 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁(yè)數(shù)： | 56/120頁(yè) |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX16-2VQ100 |
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40
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.8.3
Sensor Noise Reduction Mode
When the SM2 ... 0 bits are written to “001”, the SLEEP instruction makes the MCU enter Sen-
sor Noise Reduction mode. This sleep mode basically halts CLK
CPU, CLKFLASH and CLKI/O while
allowing the other clocks to run. The FRC-oscillator is running and supply the timers with the
CLK
CLT.
If Timer2/3 are enabled, they will keep running during sleep. The device can wake up from either
Timer Overflow, Capture event or Output Compare event from Timer2/3 if the corresponding
Timer2/3 interrupt enable bits are set in T3IMR or T2IMR register, and the Global Interrupt
Enable bit in SREG register is set.
3.8.4
Power-down Mode
When the SM2..0 bits are written to “010”, the SLEEP instruction makes the MCU enter
Power-down mode. In this mode, the FRC-oscillator, an external input clock at ECIN0/ECIN1,
Voltage monitor and the Brown-out detection are stopped (when the BODPD bit is cleared),
while the external interrupts, and the Watchdog continue operating (if enabled). Only an External
Reset, a Watchdog Reset, LF-Receiver start condition interrupt, an external level interrupt on
INT0 or INT1, or a pin change interrupt can wake up the MCU. This sleep mode basically halts
all generated clocks except SCL if enabled, allowing operation of asynchronous modules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed
level must be held for some time to wake up the MCU. Refer to Section 3.11 “External Interrupts”
on page 49 for details.
When waking up from Power-down mode, there is a delay from the wake-up condition occurs
until the wake-up becomes effective. This allows the clock to restart and become stable after
having been stopped. The wake-up period is defined by the same SUT1..0 fusebits that define
the Reset Time-out period, as described in Section 3.7.3 “Clock Sources” on page 33.
Table 3-12.
Active Clock Domains and Wake-up Sources in the Different Sleep Modes
Sleep Mode
Active Clock
Domains
Oscillators and
External Clocks
Wake-up Sources
clk
CP
U
clk
FLASH
clk
I/o
clk
CL
T
Exter
n
a
lCloc
k
FRC
SCH
SCL
IN
T0,
INT1
and
Pi
n
C
hang
e
L
F
-r
ec
ei
v
e
r
V
o
ltage
Mon
itor
Th
er
ma
lSh
utdo
wn
Sensor
Inte
rf
ace
WDT
BO
T
Time
r0
Time
r1
Time
r2
/3
IDLE
X
XX
X
XXX
Sensor Noise
Reduction
XX
X
X(1)
X
XXX
Power-down
X
X(1)
XX(2) X(2)
XX
X(2)
XXX
Notes:
1. For INT1 and INT0, only level interrupt.
2. Only, when the BODPD is set bit in the VMCSR register.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX16-2VQ100A | 40MX and 42MX FPGA Families |
| A42MX16-2VQ100B | 40MX and 42MX FPGA Families |
| A42MX16-2VQ100ES | 40MX and 42MX FPGA Families |
| A42MX16-3PQ100B | 40MX and 42MX FPGA Families |
| A42MX16-3BG100 | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-2VQ100A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2VQ100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2VQ100ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2VQ100I | 功能描述:IC FPGA MX SGL CHIP 24K 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| A42MX16-2VQ100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
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