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參數(shù)資料
| 型號： | A42MX16-2VQ100 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 71/120頁 |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX16-2VQ100 |
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54
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.12
I/O-Ports
3.12.1
Introduction
All Atmel
AVR ports have true Read-Modify-Write functionality when used as general digital
I/O ports. This means that the direction of one port pin can be changed without unintentionally
changing the direction of any other pin with the SBI and CBI instructions. The same applies
when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if
configured as input). Each output buffer has symmetrical drive characteristics with both high sink
and source capability. The pin driver is strong enough to drive LED displays directly. All port pins
have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O
pins have protection diodes to both V
CC and Ground as indicated in Figure 3-21. Refer to Sec-
tion 5.2 “Operating Characteristics of Atmel ATA6289” on page 199ff for a complete list of
electrical parameters.
Figure 3-21. I/O Pin Equivalent Schematic
All registers and bit references in this section are written in general form. A lower case “x” repre-
sents the numbering letter for the port, and a lower case “n” represents the bit number. However,
when using the register or bit defines in a program, the precise form must be used. For example,
PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Regis-
ters and bit locations are listed in Section 3.12.4 “Register Description for I/O Ports” on page 67.
Three I/O memory address locations are allocated for each port, one each for the Data Register
- PORTx, Data Direction Register - DDRx, and the Port Input Pins - PINx. The Port Input Pins
I/O location is read only, while the Data Register and the Data Direction Register are read/write.
However, writing a logic one to a bit in the PINx Register, will result in a toggle in the correspond-
ing bit in the Data Register. In addition, the Pull-up Disable - PUD bit in MCUCR disables the
pull-up function for all pins in all ports when set.
Using the I/O port as General Digital I/O is described in Section 3.12.2 “Ports as General Digital
I/O” on page 55. Most port pins are multiplexed with alternate functions for the peripheral fea-
tures on the device. How each alternate function interferes with the port pin is described in
Section 3.12.3 “Alternate Port Functions” on page 59. Refer to the individual module sections for
a full description of the alternate functions.
Note that enabling the alternate function of some of the port pins does not affect the use of the
other pins in the port as general digital I/O.
Cpin
Rpu
VBAT
Pxn
Control
Logic
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX16-2VQ100A | 40MX and 42MX FPGA Families |
| A42MX16-2VQ100B | 40MX and 42MX FPGA Families |
| A42MX16-2VQ100ES | 40MX and 42MX FPGA Families |
| A42MX16-3PQ100B | 40MX and 42MX FPGA Families |
| A42MX16-3BG100 | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-2VQ100A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2VQ100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2VQ100ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2VQ100I | 功能描述:IC FPGA MX SGL CHIP 24K 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| A42MX16-2VQ100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
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