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參數(shù)資料
| 型號： | A42MX16-3VQ100 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 12/120頁 |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX16-3VQ100 |
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109
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.13.7.8
Timer3 Input Capture Register – T3ICR
The Input Capture Register is updated with the counter value (T3CNT) each time an event
occurs on the T3ICP pin, or Timer1 output clock CLK
T1, or Timer2 output clock CLKT2, or
LF-Receiver output LFDO, or after a software capture event is generated with the T3SCE bit.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers. See Section 3.13.2 “Accessing 16-bit Registers” on page 70.
3.13.7.9
Timer3 Compare Register A – T3CORA
The Compare Registers contain a 16-bit value that is continuously compared with the counter
value (T3CNT). A match can be used to generate a Compare interrupt, a counter reset, an out-
put clock CLK
T3 or to generate a waveform with the modulator on the external output pin (T3O).
3.13.7.10
Timer3 Compare Register B – T3CORB
The Compare Registers contain a 16-bit value that is compared continuously with the counter
value (T3CNT). A match can be used to generate an Compare interrupt, a counter reset, an out-
put clock CLK
T3 or to generate a waveform with the modulator on the external output pin (T3O).
The Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written
simultaneously when the CPU writes to these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers. See Section 3.13.2 “Accessing 16-bit Registers” on page 70.
Bit
7
654
32
10
T3ICR [15..8]
T3ICRH
T3ICR [7..0]
T3ICRL
Read/Write
RR
RRR
RR
R
Initial Value
0
000
00
Bit
7
65432
10
T3CORAH [15..8]
T3CORAH
T3CORAL [7..0]
T3CORAL
Read/Write
R/W
Initial Value
0
00000
00
Bit
76
543
21
0
T3CORBH [15..8]
T3CORBH
T3CORBL [7..0]
T3CORBL
Read/Write
R/W
Initial Value
00
000
00
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX16-3VQ100A | 40MX and 42MX FPGA Families |
| A42MX16-3VQ100B | 40MX and 42MX FPGA Families |
| A42MX24-2PQ100B | 40MX and 42MX FPGA Families |
| A42MX24-2PQ100ES | 40MX and 42MX FPGA Families |
| A42MX24-2TQ100 | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-3VQ100A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3VQ100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3VQ100ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3VQ100I | 功能描述:IC FPGA MX SGL CHIP 24K 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| A42MX16-3VQ100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
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