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| 型號(hào)： | A42MX16-3VQ100 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁(yè)數(shù)： | 43/120頁(yè) |
| 文件大小： | 854K |
| 代理商： | A42MX16-3VQ100 |
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29
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.7.1.1
External Clock Monitor
If an external clock is used as system clock an internal clock monitor circuitry is activated. If the
external clock fails for a given time the ECF bit is set in the clock management status register
(CMSR). After an external clock fail is detected the system uses the internal RC oscillator (FRC)
as system clock by switching the CCS bit in the Clock Management Control Register CMCR to
zero.
The external clock monitor circuitry uses the internal SRC oscillator (90kHz) as clock source for
a 4-bit Counter. If the external clock does not reset the internal 4-Bit Counter periodically, a
counter value will be reached which triggers the external clock fail bit ECF, see Figure 3-12.
A typical time value for the external clock fail detection is 100s. Therefore the minimum external
clock frequency is limited to typically 10kHz.
An external frequency < 10kHz will force a clock fail reset.
Figure 3-12. External Clock Fail Circuitry
3.7.1.2
Clock Management Control Register – CMCR
Bit 7 - CMCCE: Clock Management Control Change Enable Bit
The CMCCE bit must be written to logic one to enable change of the CMMn bits, SRCD bit,
CMONEN, CCS bit and ECINS bit. The CMCCE bit is only updated when the other bits in CMCR
are simultaneously written to zero. CMCCE is cleared by hardware four cycles after it is written
or when CMMn, CCS and ECINS bits are written. Rewriting the CMCCE bit within this time-out
period does neither extend the time-out period, nor clear the CMCCE bit.
Bit 6 - Res: Reserved Bit
This bit is a reserved bit at the ATA6289 and will always read as zero.
Bit 5 - ECINS: External Clock INput Select Bit
This bit selects one of the two external clock input PC0(ECIN0) or PD4(ECIN1). The ECINS bit
must be written to logic one to enable the ECIN1 clock input, and if the ECINS bit is written to
logic zero, then ECIN0 clock input is enable. The ECINS bit should be only changed, when the
CCS bit is cleared. If CCS Bit is set to zero internal FRC is activated during bit change for syn-
chronization aspects.
CMCR Register
CMSR Register
Decoder
External clock
fail circuitry
4-bit Counter
Interrupt Vectors
ECF
CMM0
CMM1
MUX
ECL
C
R
FRC
SRC
CL
CMIMR Register
EXCM
ECL
Bit
765
4
3
210
CMCCE
-
ECINS
CCS
CMONEN
SRCD
CMM1
CMM0
CMCR
Read/Write
RW
R
R/W
Initial Value
000
0
000
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX16-3VQ100A | 40MX and 42MX FPGA Families |
| A42MX16-3VQ100B | 40MX and 42MX FPGA Families |
| A42MX24-2PQ100B | 40MX and 42MX FPGA Families |
| A42MX24-2PQ100ES | 40MX and 42MX FPGA Families |
| A42MX24-2TQ100 | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-3VQ100A | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3VQ100B | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3VQ100ES | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3VQ100I | 功能描述:IC FPGA MX SGL CHIP 24K 100-VQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門(mén)數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類(lèi)型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| A42MX16-3VQ100M | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:40MX and 42MX FPGA Families |
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