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參數(shù)資料
| 型號(hào)： | A42MX16-3VQ100 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁(yè)數(shù)： | 67/120頁(yè) |
| 文件大小： | 854K |
| 代理商： | A42MX16-3VQ100 |
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50
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.11.1
External Interrupt Control Register A – EICRA
The External Interrupt Control Register A contains control bits for interrupt sense control.
Bits 7..4 - Res: Reserved Bits
These bits are reserved bits at the ATA6289 and will always read as zero.
Bit 3, 2 - ISC11, ISC10: Interrupt 1 Sense Control Bit 1 and Bit 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT1 pin that activate the
interrupt are defined by ISC11 and ISC10, see Table 3-18. The value on the INT1 pin is sampled
before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one
clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an inter-
rupt. If low level interrupt is selected, the low level must be held until the completion of the
currently executing instruction to generate an interrupt.
Bit 1, 0 - ISC01, ISC00: Interrupt 0 Sense Control Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined by ISC00 and ISC01, see Table 3-19. The value on the INT0 pin is sampled
before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one
clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an inter-
rupt. If low level interrupt is selected, the low level must be held until the completion of the
currently executing instruction to generate an interrupt.
Bit
7654
3210
-
ISC11
ISC10
ISC01
ISC00
EICRA
Read/Write
RR
R/W
Initial Value
0000
Table 3-18.
Interrupt 1 Sense Control
ISC11
ISC10
Description
0
The low level of INT1 generates an interrupt request
0
1
Any logical change on INT1 generates an interrupt request
1
0
The falling edge of INT1 generates an interrupt request
1
The rising edge of INT1 generates an interrupt request
Table 3-19.
Interrupt 0 Sense Control
ISC01
ISC00
Description
0
The low level of INT0 generates an interrupt request
0
1
Any logical change on INT0 generates an interrupt request
1
0
The falling edge of INT0 generates an interrupt request
1
The rising edge of INT0 generates an interrupt request
相關(guān)PDF資料 |
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| A42MX16-3VQ100A | 40MX and 42MX FPGA Families |
| A42MX16-3VQ100B | 40MX and 42MX FPGA Families |
| A42MX24-2PQ100B | 40MX and 42MX FPGA Families |
| A42MX24-2PQ100ES | 40MX and 42MX FPGA Families |
| A42MX24-2TQ100 | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-3VQ100A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3VQ100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3VQ100ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3VQ100I | 功能描述:IC FPGA MX SGL CHIP 24K 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門(mén)數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| A42MX16-3VQ100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
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