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參數(shù)資料
| 型號： | A42MX16-3VQ100 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 89/120頁 |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX16-3VQ100 |
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70
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.13.2
Accessing 16-bit Registers
Before describing the different timers in detail we need to talk about accessing 16-bit Registers,
because
the compare registers and capture registers of Timer2 (T2ICR, T2COR) and Timer3 (T3ICR,
T3CORA, T3CORB), are 16-bit registers that can be accessed by the Atmel
AVR CPU via the
8-bit data bus. The 16-bit register must be byte accessed using two read or write operations.
Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit
access. The same temporary register is shared between all 16-bit registers within each 16-bit
timer. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of a
16-bit register is written by the CPU, the high byte stored in the temporary register, and the low
byte written are both copied into the 16-bit register in the same clock cycle. When the low byte of
a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the tempo-
rary register in the same clock cycle as the low byte is read.
Therefore to do a 16-bit write, the high byte must be written before the low byte. For a 16-bit
read, the low byte must be read before the high byte.
The following code examples show how to access the 16-bit Timer Registers assuming that no
interrupts updates the temporary register. Note that when using “C”, the compiler handles the
16-bit access.
Note:
1. The example code assumes that the part specific header file is included. For I/O Registers
located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must
be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS”
combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
The assembly code example returns the T2COR value in the r17:r16 register pair.
Assembly Code Examples(1)
...
; Set T2COR to 0x01FF
Ldi r17, 0x01
Ldi r16, 0xFF
STS T2CORH, r17
STS T2CORL, r16
; Read T2COR into r17:r16
LDS r16, T2CORL
LDS r17, T2CORH
...
C Code Examples(1)
unsigned int i;
...
/* Set T2COR to 0x01FF */
T2COR = 0x1FF;
/* Read T2COR into i */
i = T2COR;
...
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX16-3VQ100A | 40MX and 42MX FPGA Families |
| A42MX16-3VQ100B | 40MX and 42MX FPGA Families |
| A42MX24-2PQ100B | 40MX and 42MX FPGA Families |
| A42MX24-2PQ100ES | 40MX and 42MX FPGA Families |
| A42MX24-2TQ100 | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-3VQ100A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3VQ100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3VQ100ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3VQ100I | 功能描述:IC FPGA MX SGL CHIP 24K 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| A42MX16-3VQ100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
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