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參數(shù)資料
| 型號： | a8251 |
| 廠商： | Altera Corporation |
| 英文描述： | Programmable Communications Interface(可編程通信接口) |
| 中文描述： | 可編程通信接口（可編程通信接口） |
| 文件頁數(shù)： | 12/21頁 |
| 文件大?。?/td> | 338K |
| 代理商： | A8251 |
36
Altera Corporation
a8251 Programmable Communications Interface Data Sheet
For example, after detecting a logic low in divide-by-1 mode, the
a8251
assumes data is available on the next rising edge. However, after
detecting a logic low in divide-by-16 mode, the
a8251
counts 8
nrxc
edges and samples again. The data must still be a logic low. At this point,
the
a8251
assumes the data and clock are synchronized, and samples
data every 16 clock edges thereafter. Divide-by-64 mode is similar to
divide-by-16, with the start bit sampled at the first rising edge and the
32nd rising edge of
nrxc
. Data is then sampled every 64 rising edges.
Data Bit Sampling
After detecting a start bit, the
a8251
samples and shifts the data into the
shift register. Data bit sampling occurs on every rising edge in divide-by-
1 mode, every 16 rising edges in divide-by-16 mode, and every 64 rising
edges in divide-by-64 mode. Each time a bit is sampled, parity is
calculated for future error detection. See
Figure 3
.
Figure 3. Receiver Clock Signals
Parity/Stop Bit Detection
The
a8251
counts the number of data bits as it shifts. When the number
of data bits received matches the number specified in the control register,
the
a8251
expects either a parity bit or a stop bit.
If parity is enabled, the
a8251
samples for the parity bit, which is
processed for parity but is not shifted into the shift register. After the
parity bit, or after the last data bit if parity is not enabled, the
a8251
expects a stop bit (i.e., logic high). If a logic low is sampled, the
fe
bit is
set in the status register.
The
a8251
receives data with one or two stop bits. If one stop bit is
specified in the control register, the
a8251
will expect one stop bit before
starting the synchronization process. Similarly, if two stop bits are
specified, the synchronization process begins after detecting two logic
highs.
nrxc (Divide-by-1)
nrxc (Divide-by-16)
Sampling Pulse
(Divide-by-16)
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