參數(shù)資料
型號(hào)： a8251
廠商： Altera Corporation
英文描述： Programmable Communications Interface(可編程通信接口)
中文描述： 可編程通信接口（可編程通信接口）
文件頁(yè)數(shù)： 5/21頁(yè)
文件大?。?/td> 338K
代理商： A8251
Altera Corporation
29
a8251 Programmable Communications Interface Data Sheet
Baud Rate Factor
Bits 0 and 1 (
b1
,
b2
) of the MIR are the baud rate factor bits, which
determine the ratio between the data rate and the clocks. The ratios are
identical when transmitting and receiving. The baud rate factor bits also
provide a means of programming the
a8251
for synchronous operation.
Table 3
shows the logic level of the baud rate factor bits and the
corresponding programmed function.
Word Length Select
Bits 2 and 3 (
l1
,
l2
) of the MIR are the word length select bits, which are
used to select the character length of the data byte.
Table 4
shows the logic
level of the word length select bits and the corresponding word length.
Table 3. Baud Rate Factor Bits
b2
b1
Programmed Function
0
0
0
1
Synchronous operation.
Divide-by-1 mode. Clock and data rates are identical. External
logic is responsible for synchronizing the
rxd
signal to the
nrxc
signal. The
rxd
signal is sampled on the rising edge of
the
nrxc
signal, and the
txd
signal is asserted on the falling
edge of the
ntxc
signal.
Divide-by-16 mode. The clock rate is 16 times the data rate.
After start bit detection (
rxd
low), the
rxd
signal is sampled on
the ninth rising edge of
nrxc
. After writing to the transmitter
register, the
txd
signal is asserted on the first falling edge of
the
ntxc
signal and every 16 clocks thereafter.
Divide-by-64 mode. The clock rate is 64 times the data rate.
After start bit detection (
rxd
low), the
rxd
signal is sampled on
the 33rd rising edge of the
nrxc
. After writing to the transmitter
register (assuming the transmission is enabled),
txd
is
asserted on the first falling edge of the
ntxc
signal and every
64 clocks thereafter.
1
0
1
1
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