參數(shù)資料
型號(hào)： a8251
廠商： Altera Corporation
英文描述： Programmable Communications Interface(可編程通信接口)
中文描述： 可編程通信接口（可編程通信接口）
文件頁(yè)數(shù)： 2/21頁(yè)
文件大小： 338K
代理商： A8251
26
Altera Corporation
a8251 Programmable Communications Interface Data Sheet
Table 1
describes input and output ports of the
a8251
.
Table 1. a8251 Ports (Part 1 of 2)
Name
Type
Polarity
Description
clk
Input
Input
–
–
Master clock input.
Control/data select. When the
selects status/control data to read/write; otherwise, the microprocessor
selects receiver/transmitter data to read/write.
Parallel data input from the microprocessor or other controlling device.
External sync detect. In synchronous designs, when the
is asserted, the
a8251
begins receiving data on the next rising edge of the
nrxc
signal.
Chip select from the microprocessor. When the
read or write operations are enabled.
Clear to send, typically a modem signal name. When the
asserted, and if the
txen
bit of the command instruction register is set, data
transmission is enabled.
Data set ready, typically a modem signal name. The state of this input may
be tested by reading status register bit 7 (
Read control for the registers. When the
low, the microprocessor reads from the registers.
Receive clock. The receiver control logic samples the
state of the
nrxc
signal and the baud rate factor bits in the mode instuction
register.
Transmit clock. Data is asserted to the
Write control for the registers. When the
low, the microprocessor writes to the registers.
Asynchronous reset for the registers and control logic.
Receive data. Serial input from the modem or peripheral.
Parallel data output to the microprocessor or other controlling device.
Data terminal ready, typically a modem signal name. Bit 1 of the command
instruction register sets the
ndtr
signal.
Output enable for the output data bus. When the
output data is enabled on the
dout[7..0]
Request to send, typically a modem signal name. Bit 5 of the command
instruction register sets the
nrts
signal.
Receiver ready. A high
rxrdy
signal indicates that the
a character to be read by the microprocessor.
Sync/break detect. In synchronous operation, when the
is asserted, the
a8251
begins receiving data on the next rising edge of the
nrxc
signal. In asynchronous operation,
condition on
rxd
.
cnd
cnd
signal goes high, the microprocessor
din[7..0]
Input
Input
–
extsyncd
High
extsyncd
signal
ncs
Input
Low
ncs
signal is asserted, all
ncts
Input
Low
ncts
signal is
ndsr
Input
Low
dsr
).
nrd
Input
Low
nrd
and the
ncs
signals are both
nrxc
Input
Low
nrxd
based on the
ntxc
Input
Input
Low
Low
txd
on the falling edge of
and the
ncs
ntxc
.
nwr
nwr
signals are both
nreset
Input
Input
Output
Output
Low
–
Low
Low
rxd
dout[7..0]
ndtr
nen
Output
Low
nen
signal is asserted, the
bus line.
nrts
Output
Low
rxrdy
Output
High
a8251
has received
syn_brk
Output
High
extsyncd
signal
syn_brk
indicates a break
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