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參數(shù)資料
| 型號： | a8251 |
| 廠商： | Altera Corporation |
| 英文描述： | Programmable Communications Interface(可編程通信接口) |
| 中文描述： | 可編程通信接口（可編程通信接口） |
| 文件頁數(shù)： | 15/21頁 |
| 文件大?。?/td> | 338K |
| 代理商： | A8251 |
Altera Corporation
39
a8251 Programmable Communications Interface Data Sheet
Figure 5. Transmitter Control & Error Signals (Asynchronous)
The X indicates “don’t care.”
Transmitter Start Bit
When data is transferred to the shift register, a start bit (i.e., logic low) is
placed on the
txd
signal on the falling edge of the
ntxc
signal. The start
bit value remains active for the number of clock cycles specified by the
divide-by mode (i.e., 1, 16, or 64). See
Figure 6
.
Figure 6. Transmitter Data & Clock Signals
Transmitter Data
After the start bit is transmitted, the data bits shift out of the TBR one at a
time, from the least significant to the most significant. The cycle time for
each bit starts at the beginning of the clock cycle, which depends on the
specified divide-by mode. The number of bits shifted out corresponds to
the number of bits specified in the MIR.
ncts
txempty
First
Data Bit
Second
Data Bit
Third
Data Bit
X
X
X
X
X
X
txrdy
(Status Bit)
txrdy
(Pin)
cnd
nwr
txd
ntxc (Divide-by-16)
Start Bit
Data Bit
ntxc (Divide-by-1)
txd
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