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參數(shù)資料
| 型號(hào)： | a8251 |
| 廠商： | Altera Corporation |
| 英文描述： | Programmable Communications Interface(可編程通信接口) |
| 中文描述： | 可編程通信接口（可編程通信接口） |
| 文件頁數(shù)： | 13/21頁 |
| 文件大?。?/td> | 338K |
| 代理商： | A8251 |
Altera Corporation
37
a8251 Programmable Communications Interface Data Sheet
Error Detection
Three errors can occur when the
a8251
is receiving: framing, overrun,
and parity. Refer to
Table 9 on page 33
of this data sheet for error
definitions.
Receiver Buffer Register Transfer
Once the last stop bit is received, or a framing error is detected, the data
in the shift register is transferred to the RBR. At this point, all status bits
associated with this data word are set, including the
rxrdy
bit. The
receiver process concludes when the microprocessor reads data from the
RBR.
Break Detection
In asynchronous operation, the
syn_brk
signal indicates that the receiver
has detected a break condition. A break condition is defined as the
condition when the
rxd
signal is continuously low, i.e., for an entire
character sequence including start, stop, and parity bits. The
syn_brk
bit
can be reset by a total state reset operation or by the
rxd
signal returning
to a logic high. See
Figure 4
.
Figure 4. Receiver Control & Error Signals (Asynchronous)
The X indicates “don’t care.”
Second Data Bit Lost
syn_brk
fe
oe
rxrdy
nwr
nrd
rxd
First
Data Bit
Second
Data Bit
Third
Data Bit
X
X
X
X
X
cnd
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