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參數(shù)資料
| 型號： | a8251 |
| 廠商： | Altera Corporation |
| 英文描述： | Programmable Communications Interface(可編程通信接口) |
| 中文描述： | 可編程通信接口（可編程通信接口） |
| 文件頁數(shù)： | 16/21頁 |
| 文件大?。?/td> | 338K |
| 代理商： | A8251 |
40
Altera Corporation
a8251 Programmable Communications Interface Data Sheet
Transmitter Parity Bit
If parity is enabled, the bit following the last data bit is the parity bit.
The parity bit has a value that forces the entire data byte to have the
correct parity. For example, if parity is set to odd in the MIR, then the
parity bit guarantees there are an odd number of 1s (i.e., data plus
the parity bit). If parity is set to even, then the parity bit guarantees
there are an even number of 1s.
Transmitter Stop Bit
After the parity bit is transmitted, or the last data bit if parity is not
enabled, one or two stop bits are transmitted on the
txd
output. The
output then stays high until the beginning of the next data word
transmission.
Receiver Operation (Synchronous)
When the
a8251
is programmed for synchronous operation, start or
stop bits are not added to the data word. Instead the
rxd
signal is
synchronous to the receive clock (
nrxc
signal), and the data stream
is synchronized to the receiving
a8251
by the recognition of a sync
character or characters. See
Figure 7
.
Figure 7. Receiver Control & Error Signals (Synchronous)
The X indicates “don’t care.”
extsyncd
syn_brk
(Status Bit)
rxrdy
(Pin)
X
X
X
X
Data Characters
Two
One
Three
Sync Characters
One
Two
Sync Characters
One
Two
Parity Bit
Parity Bit
Parity Bit
Parity Bit
nrxd
oe
(Status Bit)
Data Character Two Lost
cnd
nwr
nrd
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