TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltages (AVDD, DVDD)
+5.0
V
Ambient Temperature
25
°C
Input Clock (FMCLK)
27.1656
MHz
Input Signal
1001.2938 Hz
–0.5
dB Full Scale
Input Sample Rate
44.1
kHz
Measurement Bandwidth
10 Hz to 20 kHz
Input Data Word Width
18
Bits
Load Capacitance
100
pF
Input Voltage HI (VIH)
2.4
V
Input Voltage LO (VIL)
0.8
V
NOTES
I
2S-Justified Mode (Ref. Figure 3).
Device Under Test (DUT) is bypassed, decoupled and dc-coupled as shown in Figure 17 (no de-emphasis circuit).
Performance of the right and left channels are identical (exclusive of “Interchannel Gain Mismatch” and “Interchannel Phase Deviation” specifications).
Attenuation setting is 0 dB.
Values in bold typeface are tested; all others are guaranteed, not tested.
ANALOG PERFORMANCE
Min
Typ
Max
Units
Resolution
18
Bits
Dynamic Range (20 to 20 kHz, –60 dB Input)
(No A-Weight Filter)
85.7
91
dB
(With A-Weight Filter)
88
94
dB
Total Harmonic Distortion + Noise
–88
–84
dB
0.004
0.0063
%
Analog Outputs
Single-Ended Output Range (
±Full Scale)
2.8
3.0
3.2
V p-p
Output Impedance at Each Output Pin
17
24
Output Capacitance at Each Output Pin
20
pF
External Load Impedance (THD +N
≤ –84 dB)
750
2K
Out-of-Band Energy (0.5
× F
S to 100 kHz)
–72.5
dB
CMOUT
2.05
2.25
2.45
V
DC Accuracy
Gain Error
±1
5
%
Interchannel Gain Mismatch
0.01
0.225
dB
Gain Drift
140
270
ppm/
°C
Interchannel Crosstalk (EIAJ Method)
101
dB
Interchannel Phase Deviation
±0.1
Degrees
Attenuator Step Size
0.6
1.0
1.4
dB
Attenuator Range Span
–61.5
–62.5
–63.5
dB
Mute Attenuation
–70
–74.2
dB
De-Emphasis Switch (EMPL, EMPR) DC Resistance
3
10
50
DIGITAL INPUTS
Min
Typ
Max
Units
Input Voltage HI (VIH)
2.4
V
Input Voltage LO (VIL)
0.8
V
Input Leakage (IIH @ VIH = 2.4 V)
1
6
A
Input Leakage (IIL @ VIL = 0.8 V)
1
6
A
Input Capacitance
20
pF
REV. A
–2–
AD1859–SPECIFICATIONS