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參數(shù)資料
| 型號： | AD1859JRZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/16頁 |
| 文件大小： | 0K |
| 描述： | IC DAC STEREO SGL SUPP 5V 28SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | AD1859 Discontinuation 12/Apr/2012 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 18 |
| 數(shù)據(jù)接口： | DSP，I²S，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 330mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸出數(shù)目和類型： | 2 電壓，單極 |
| 采樣率（每秒）： | * |
| 其它名稱： | AD1859JRZ-RLDKR |
REV. A
–6–
AD1859
Analog Signals
Pin Name
Number
I/O
Description
FILT
28
O
Voltage reference filter capacitor
connection. Bypass and decouple
the voltage reference with paral-
lel 10
F and 0.1 F capacitors
to the FGND pin.
FGND
27
I
Voltage reference filter ground.
Use exclusively for bypassing and
decoupling of the FILT pin
(voltage reference).
CMOUT
1
O
Voltage reference common-mode
output. Should be decoupled
with 10
F capacitor to the AGND
pin or plane. This output is available
externally for dc-coupling and level-
shifting. CMOUT should not have
any signal dependent load, or where
it will sink or source current.
OUTL
4
O
Left channel line level analog output.
OUTR
25
O
Right channel line level analog output.
EMPL
3
O
De-emphasis switch connection
for the left channel. Can be left
unconnected if de-emphasis is not
required in the target application.
EMPR
26
O
De-emphasis switch connection
for the right channel. Can be left
unconnected if de-emphasis is not
required in the target application.
Control and Clock Signals
Pin Name
Number
I/O
Description
PD/RST
11
I
Power down/reset. The AD1859 is
placed in a low power consumption
“sleep” mode when this pin is held
LO. The AD1859 is reset on the
rising edge of this signal. The serial
control port registers are reset to
their default values. Connect HI
for normal operation.
DEEMP
2
I
De-emphasis. An external analog de-
emphasis circuit network is enabled
when this input signal is HI. This
circuit is typically used to impose a
50/15
s (or perhaps the CCITT
J.17) response characteristic on the
output audio spectrum.
MUTE
7
I
Mute. Assert HI to mute both
stereo analog outputs of the AD1859.
Deassert LO for normal operation.
XTALI/
MCLK
16
I
Crystal input or master clock input.
Connect to one side of a quartz
crystal to this input, or connect to
an external clock source to over-
drive the on-chip oscillator.
XTALO
15
O
Crystal output. Connect to other
side of a quartz crystal. Do not con-
nect if using the XTALI/MCLK
pin with an external clock source.
Power Supply Connections and Miscellaneous
Pin Name
Number
I/O
Description
AVDD
23
I
Analog Power Supply. Connect
to analog +5 V supply.
AGND
6
I
Analog Ground.
DVDD
17
I
Digital Power Supply. Connect
to digital +5 V supply.
DGND
18
I
Digital Ground.
NC
5, 22, 24
No Connect. Reserved. Do not
connect.
PIN DESCRIPTIONS
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD1860N | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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| AD1860N-K | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD1860R | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD1860R-J | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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