參數資料
型號: AD1859JRZ-RL
廠商: Analog Devices Inc
文件頁數: 2/16頁
文件大小: 0K
描述: IC DAC STEREO SGL SUPP 5V 28SOIC
產品培訓模塊: Data Converter Fundamentals
DAC Architectures
產品變化通告: AD1859 Discontinuation 12/Apr/2012
標準包裝: 1
位數: 18
數據接口: DSP,I²S,串行,SPI?
轉換器數目: 2
電壓電源: 模擬和數字
功率耗散(最大): 330mW
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應商設備封裝: 28-SOIC W
包裝: 標準包裝
輸出數目和類型: 2 電壓,單極
采樣率(每秒): *
其它名稱: AD1859JRZ-RLDKR
REV. A
–10–
AD1859
D6
CCLK
CDATA
CLATCH
D7
D6
D5
D4
D3
D2
D1
D0
D7
D5
MSB
LSB
MSB
Figure 7. Serial Control Port Timing
DATA6
Mute
DATA5
Atten5
DATA4
Atten4
DATA3
Atten3
DATA2
Atten2
DATA1
Atten1
DATA0
Atten0
Right Channel = HI
Left Channel = LO
Mute = HI
Normal = LO
00 0000 = 0.0dB
00 0001 = –1.0dB
00 0010 = –2.0dB
00 0011 = –3.0dB
00 0100 = –4.0dB
00 0101 = –5.0dB
00 0110 = –6.0dB
00 0111 = –7.0dB
00 1000 = –8.0dB
*
11 1101 = –61.0dB
11 1110 = –62.0dB
11 1111 = –63.0dB
LSB
MSB
DATA7
LEFT/RIGHT
Figure 8. Serial Control Bit Definitions
The serial control port is byte oriented. The data is MSB first,
and is unsigned. There is a control register for the left channel
and a control register for the right channel, as distinguished by
the MSB (DATA7). The bits are assigned as shown in Figure 8.
The left channel control register and the right channel control reg-
ister have identical power up and reset default settings. DATA6,
the Mute control bit, reset default state is LO, which is the nor-
mal (nonmuted) setting. DATA5:0, the Atten5 through Atten0
control bits, have a reset default value of 00 0000, which is an
attenuation of 0.0 dB (i.e., full scale, no attenuation). The intent
with these reset defaults is to enable AD1859 applications with-
out requiring the use of the serial control port. For those users
that do not use the serial control port, it is still possible to mute
the AD1859 output by using the external MUTE (Pin 7) signal.
It is recommended that the output be muted for approximately
1000 input sample periods during power-up or following any
radical sample rate change (>5%) to allow the digital phase
locked loop to settle.
Note that the serial control port timing is asynchronous to the
serial data input port timing. Changes made to the attenuator
level will be updated on the next edge of the LRCLK after the
CLATCH write pulse. The AD1859 has been designed to re-
solve the potential for metastability between the LRCLK edge
and the CLATCH write pulse rising edge. The attenuator set-
ting is guaranteed to be valid even if the LRCLK edge and the
CLATCH rising edge occur essentially simultaneously.
On-Chip Oscillator and Master Clock
The asynchronous master clock of the AD1859 can be supplied
by either an external clock source applied to XTALI/MCLK or
by connecting a crystal across the XTALI/MCLK and XTALO
pins, and using the on-chip oscillator. If a crystal is used, it
should be fundamental-mode and parallel-tuned. Figure 9
shows example connections.
The range of audio sample rates (as determined from the
LRCLK input) supported by the AD1859 is a function of the
master clock rate (i.e., the crystal frequency or external clock
source frequency) applied. The highest sample rate supported
can be computed as follows:
Highest Sample Rate = Master Clock Frequency
÷ 512
The lowest sample rate supported can be computed as follows:
Lowest Sample Rate = Master Clock Frequency
÷ 1024
27MHz
27MHz OSCILLATOR CONNECTION
XTALI/MCLK
XTALO
AD1859
NC
20-64pF
27MHz
27MHz CRYSTAL CONNECTION
XTALI/MCLK
XTALO
AD1859
Figure 9. Crystal and Oscillator Connections
Figure 10 illustrates these relations. As can be seen in Figure 10,
a 27 MHz MCLK or crystal frequency supports audio sample
rates from approximately 28 kHz to 52 kHz.
76
20
36
28
44
52
60
68
20
18
34
30
28
24
22
26
32
36
XTAL/MCLK FREQUENCY – MHz
HIGHEST
L/R SAMPLE RATE
(MCLK/512)
LOWEST
L/R SAMPLE RATE
(MCLK/1024)
L/R
CLOCK
SAMPLE
FREQUENCY
kHz
Figure 10. MCLK Frequency vs. L/R Clock Frequency
Mute and Attenuation
The AD1859 offers two methods of muting the analog output.
By asserting the MUTE (Pin 7) signal HI, both the left channel
and the right channel are muted. As an alternative, the user can
assert the mute bit in the serial control registers HI for indi-
vidual mute of either the left channel or the right channel. The
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