參數(shù)資料
型號(hào)： AD1859JRZ-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 5/16頁(yè)
文件大小： 0K
描述： IC DAC STEREO SGL SUPP 5V 28SOIC
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告： AD1859 Discontinuation 12/Apr/2012
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 18
數(shù)據(jù)接口： DSP，I²S，串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 330mW
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC W
包裝： 標(biāo)準(zhǔn)包裝
輸出數(shù)目和類型： 2 電壓，單極
采樣率（每秒）： *
其它名稱： AD1859JRZ-RLDKR
AD1859
REV. A
–13–
PCB and Ground Plane Recommendations
The AD1859 ideally should be located above a split ground
plane, with the digital pins over the digital ground plane, and
the analog pins over the analog ground plane. The split should
occur between Pins 6 and 7 and between Pins 22 and 23 as
shown in Figure 19. The ground planes should be tied together
at one spot underneath the center of the package with an ap-
proximately 3 mm trace. This ground plane strategy minimizes
RF transmission and reception as well as maximizes the AD1859’s
analog audio performance.
13
1
2
5
6
7
3
4
8
9
10
11
12
14
18
28
27
24
23
22
26
25
21
20
19
17
16
15
CMOUT
DEEMP
NC
EMPL
OUTL
AGND
MUTE
18/16
IDPM0
IDPM1
SDATA
LRCLK
BCLK
PD/RST
ANALOG
GROUND PLANE
DIGITAL
GROUND PLANE
FILT
FGND
NC
AVDD
NC
EMPR
OUTR
CLATCH
CDATA
CCLK
DGND
DVDD
XTALI/MCLK
XTALO
Figure 19. Recommended Ground Plane
TIMING DIAGRAMS
The serial data port timing is shown in Figures 20 and 21. The
minimum bit clock HI pulse width is tDBH, and the minimum bit
clock LO pulse width is tDBL. The minimum bit clock period is
tDBP. The left/right clock minimum setup time is tDLS, and the
left/right clock minimum hold time is tDLH. The serial data mini-
mum setup time is tDDS, and the minimum serial data hold time
is tDDH.
BCLK
SDATA
LEFT-
JUSTIFIED
MODE
SDATA
RIGHT-
JUSTIFIED
MODE
SDATA
I2S-
JUSTIFIED
MODE
MSB
LSB
tDBH
tDBP
tDBL
tDLS
tDDS
tDDH
tDDS
tDDH
tDDS
tDDH
tDDS
tDDH
MSB
MSB-1
L
RCLK
Figure 20. Serial Data Port Timing
tDBH
tDBL
tDLS
tDDH
tDDS
BCLK
SDATA
LEFT-JUSTIFIED
DSP SERIAL
PORT STYLE
MODE
MSB
MSB-1
tDBP
tDLH
LRCLK
Figure 21. Serial Data Input Port Timing DSP Serial
Port Style
The serial control port timing is shown in Figure 22. The mini-
mum control clock HI pulse width is tCCH, and the minimum
control clock LO pulse width is tCCL. The minimum control
clock period is tCCP. The control data minimum setup time is
tCSU, and the minimum control data hold time is tCHD. The
minimum control latch delay is tCLD, the minimum control latch
LO pulse width is tCLL, and the minimum control latch HI pulse
width is tCLH.
CCLK
tCCL
tCCP
tCCH
CDATA
tCSU
tCHD
CLATCH
tCLD
tCLH
tCLL
LSB
Figure 22. Serial Control Port Timing
The master clock (or crystal input) and power down/reset tim-
ing is shown in Figure 23. The minimum MCLK period is tMCP,
which determines the maximum MCLK frequency at FMC. The
minimum MCLK HI and LO pulse widths are tMCH and tMCL,
respectively. The minimum reset LO pulse width is tPDRP (four
XTALI/MCLK periods) to accomplish a successful AD1859 re-
set operation.
PD/RST
XTALI/MCLK
tPDRP
tMCH
tMCP
tMCL
Figure 23. MCLK and Power Down/Reset Timing
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD1860N 制造商:Rochester Electronics LLC 功能描述:- Bulk
AD1860N-J 制造商:Rochester Electronics LLC 功能描述:- Bulk
AD1860N-K 制造商:Rochester Electronics LLC 功能描述:- Bulk
AD1860R 制造商:Rochester Electronics LLC 功能描述:- Bulk
AD1860R-J 制造商:Rochester Electronics LLC 功能描述:- Bulk
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