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參數(shù)資料
| 型號(hào)： | AD1859JRZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 16/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC STEREO SGL SUPP 5V 28SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | AD1859 Discontinuation 12/Apr/2012 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 18 |
| 數(shù)據(jù)接口： | DSP，I²S，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 330mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸出數(shù)目和類型： | 2 電壓，單極 |
| 采樣率（每秒）： | * |
| 其它名稱： | AD1859JRZ-RLDKR |
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AD1859
REV. A
–9–
Figure 3 shows the I
2S-justified mode. LRCLK is LO for the left
channel, and HI for the right channel. Data is valid on the rising
edge of BCLK. The MSB is left-justified to an LRCLK transition
but with a single BCLK period delay. The I
2S-justified mode
can be used in either the 16-bit or the 18-bit input mode.
Figure 4 shows the left-justified mode. LRCLK is HI for the
left channel, and LO for the right channel. Data is valid on the
rising edge of BCLK. The MSB is left-justified to an LRCLK
transition, with no MSB delay. The left-justified mode can be
used in either the 16-bit or the 18-bit input mode.
Figure 5 shows the left-justified DSP serial port style mode.
LRCLK must pulse HI for at least one bit clock period before
the MSB of the left channel is valid, and LRCLK must pulse HI
again for at least one bit clock period before the MSB of the
right channel is valid. Data is valid on the falling edge of
BCLK. The left-justified DSP serial port style mode can be
used in either the 16-bit or the 18-bit input mode. Note that in
this mode, it is the responsibility of the DSP to ensure that the
left data is transmitted with the first LRCLK pulse, and that the
right data is transmitted with the second LRCLK pulse, and
that synchronism is maintained from that point forward.
Note that in 16-bit input mode, the AD1859 is capable of a 32
× F
S BCLK frequency “packed mode” where the MSB is left-
justified to an LRCLK transition, and the LSB is right-justified
to an LRCLK transition. LRCLK is HI for the left channel,
and LO for the right channel. Data is valid on the rising edge of
BCLK. Packed mode can be used when the AD1859 is pro-
grammed in either right-justified or left-justified mode. Packed
mode is shown in Figure 6.
Serial Control Port
The AD1859 serial control port is SPI compatible. SPI
(Serial Peripheral Interface) is a serial port protocol popularized
by Motorola’s family of microcomputer and microcontroller
products. The write-only serial control port gives the user ac-
cess to channel specific mute and attenuation. The AD1859
serial control port consists of three signals, control clock CCLK
(Pin 19), control data CDATA (Pin 20), and control latch
CLATCH (Pin 21). The control data input (CDATA) must be
valid on the control clock (CCLK) rising edge, and the control
clock (CCLK) must only make a LO to HI transition when
there is valid data. The control latch (CLATCH) must make a
LO to HI transition after the LSB has been clocked into the
AD1859, while the control clock (CCLK) is inactive. The tim-
ing relation between these signals is shown in Figure 7.
MSB-1
MSB-2
LSB+2
LSB+1
LSB
MSB
MSB-1
MSB-2
LSB
LSB+2
LSB+1
LEFT CHANNEL
RIGHT CHANNEL
MSB
BCLK
INPUT
SDATA
INPUT
LRCLK
INPUT
Figure 3. I2S-Justified Mode
MSB-1
MSB-2
LSB+2
LSB+1
LSB
MSB
MSB-1
MSB-2
LSB
LSB+2
LSB+1
LEFT CHANNEL
RIGHT CHANNEL
MSB
MSB-1
MSB
BCLK
INPUT
SDATA
INPUT
LRCLK
INPUT
Figure 4. Left-Justified Mode
BCLK
INPUT
SDATA
INPUT
MSB
MSB-1
LSB+2
LSB+1
LSB
MSB
MSB-1
LSB
LSB+2
LSB+1
LEFT CHANNEL
RIGHT CHANNEL
MSB
MSB-1
LRCLK
INPUT
Figure 5. Left-Justified DSP Serial Port Style Mode
BCLK
INPUT
SDATA
INPUT
MSB-1
MSB-2
LSB+2
LSB+1
LSB
MSB
MSB-1
MSB-2
LSB
LSB+2
LSB+1
MSB
MSB-1
LSB
LEFT CHANNEL
RIGHT CHANNEL
MSB
LRCLK
INPUT
Figure 6. 32
× F
S Packed Mode
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AD1860N | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD1860N-J | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD1860N-K | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD1860R | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD1860R-J | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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