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參數(shù)資料
| 型號： | AD568JQ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/14頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT HS MONO 35NS 24CDIP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時間： | 35ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-CDIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 24-CDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電流，單極；1 電流，雙極；1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | * |
AD568
REV. A
–6–
sation capacitor across the 1 k
feedback resistor produces opti-
mal settling. Lower noise gain can be achieved by connecting RL
to IOUT, increasing the DAC output impedance to approximately
200
, and reducing the noise gain to 6 (illustrated in Figure 9).
While the output in this configuration will feature improved
noise performance, it is somewhat less stable and may suffer
from ringing. The compensation capacitance should be in-
creased to 7 pF to maintain stability at this reduced gain.
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8
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AD568
+15V
REFCOM
–15V
IBPO
RL
ACOM
LCOM
SPAN
THCOM
VTH
IOUT
DIGITAL
INPUTS
0.2F
0.1F
–15V
+15V
ANALOG
GND PLANE
DIGITAL
GND PLANE
DIGITAL
SUPPLY
GROUND
100pF
+5V
ANALOG
OUTPUT
ANALOG
SUPPLY
GROUND
5pF
–VS
+VS
100
RTH
1k
AD840
AMPLIFIER NOISE GAIN: 11
Figure 8. Unipolar Output Buffered 0 to –10.24V
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AD568
+15V
REFCOM
–15V
IBPO
RL
ACOM
LCOM
SPAN
THCOM
VTH
IOUT
DIGITAL
INPUTS
0.2F
0.1F
–15V
+15V
ANALOG
GND PLANE
DIGITAL
GND PLANE
DIGITAL
SUPPLY
GROUND
100pF
+5V
ANALOG
OUTPUT
ANALOG
SUPPLY
GROUND
7pF
–VS
+VS
200
RTH
1k
AD840
AMPLIFIER NOISE GAIN: 6
Figure 9. Bipolar Output Buffered
±5.12 V
Bipolar Inverting Configuration
Figure 9 illustrates the implementation of a +5.12 V to –5.12 V
bipolar range, achieved by connecting the bipolar offset current,
IBPO, to the summing junction of the external amplifier. Note
that since the amplifier is providing an inversion, the full-scale
output voltage is –5.12 V, while the bipolar offset voltage (all
bits OFF) is +5.12 V at the amplifier output.
Noninverting Configuration
If a positive full-scale output voltage is required, it can be imple-
mented using the AD568 in the unbuffered voltage output mode
followed by the AD840 in a noninverting configuration (Figure
10). The noise gain of this topology is 10, requiring only 5 pF
across the feedback resistor to optimize settling.
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10
9
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1
2
3
4
7
6
5
AD568
+15V
REFCOM
–15V
IBPO
RL
ACOM
LCOM
SPAN
THCOM
VTH
IOUT
DIGITAL
INPUTS
0.2F
0.1F
–15V
+15V
ANALOG
GND
PLANE
DIGITAL
SUPPLY
GROUND
100pF
+5V
ANALOG
OUTPUT
ANALOG
SUPPLY
GROUND
5pF
–VS
+VS
111
RTH
1k
AD840
AMPLIFIER NOISE GAIN: 10
DIGITAL GND PLANE
Figure 10. Unipolar Output Buffered 0 V to +10.24 V
Guidelines for Using the AD568
The designer who seeks to combine high speed with high preci-
sion faces a challenging design environment. Where tens of
milliamperes are involved, fractions of an ohm of misplaced
impedance can generate several LSBs of error. Increasing
bandwidths make formerly negligible parasitic capacitances and
inductances significant. As system performance reaches and ex-
ceeds that of the measurement equipment, time-honored test
methods may no longer be trustworthy. The DAC’s placement
on the boundary between the analog and digital domains intro-
duces additional concerns. Proper RF techniques must be used
in board design, device selection, supply bypassing, grounding,
and measurement if optimal performance is to be realized. The
AD568 has been configured to be relatively easy to use, even in
some of the more treacherous applications. The device charac-
teristics shown in this data sheet are readily achievable if proper
attention is paid to the details. Since a solid understanding of
the circuit involved is one of the designer’s best weapons against
the difficulties of RF design, the following sections provide illus-
trations, explanations, examples, and suggestions to facilitate
successful design with the AD568.
Current Output vs. Voltage Output
As indicated in Figures 3 through 10, the AD568 has been
designed to operate in several different modes depending on the
external circuit configuration. While these modes may be
categorized by many different schemes, one of the most impor-
tant distinctions to be made is whether the DAC is to be used to
generate an output voltage or an output current. In the current
output mode, the DAC output (Pin 20) is tied to some type of
summing junction, and the current flowing from the DAC into
this summing junction is sensed (e.g., Figures 8 and 9). In this
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| AD568KQ | 功能描述:IC DAC 12BIT HS MONO 35NS 24CDIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD568S | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit Ultrahigh Speed Monolithic D/A Converter |
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| AD568SQ | 功能描述:數(shù)模轉(zhuǎn)換器- DAC IC MONO 12-BIT D/A CONV RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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