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| 型號(hào)： | AD568JQ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 2/14頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT HS MONO 35NS 24CDIP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時(shí)間： | 35ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-CDIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 24-CDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電流，單極；1 電流，雙極；1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | * |
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AD568
REV. A
–10–
Circuit layout for a high speed SHA is almost as critical as the
design itself. Figure 17 shows a recommended layout of the
deglitching cell for a double sided printed circuit board. The
layout is very compact with care taken that all critical signal
paths are short.
–5V
MC
10124
249
169
510
360
360
–5V
169
249
500pF
OUTPUT
75
200
200
IN4735
+15V
–15V
20k
1.6
0.39F
TO PIN 2
SD5000
100pF
4
5
10
11
9
16
14
13
12
6
8
5
4
3
1
AD841
Figure 17. High Performance Deglitcher
Grounding Rules
The AD568 brings out separate reference, output, and digital
power grounds. This allows for optimum management of signal
ground currents for low noise and high-speed-settling perfor-
mance. The separate ground returns are provided to minimize
changes in current flow in the analog signal paths. In this way,
logic return currents are not summed into the same return path
with the analog signals.
It is important to understand which supply and signal currents
are flowing in which grounds so that they may be returned to
the proper power supply in the best possible way.
The majority of the current that flows into the VCC supply (Pin
24) flows out (depending on the DAC input code) either the
ANALOG COMMON (Pin 18), the LADDER COMMON
(Pin 17), and/or IOUT (Pin 20).
The current in the LADDER COMMON is configured to be
code independent when the output current is being summed
into a virtual ground. If IOUT is operated into its own output im-
pedance (or in any unbuffered voltage output mode) the current
in LADDER COMMON will become partially code dependent.
The current in the ANALOG COMMON (Pin 18) is an ap-
proximate complement of the current in IOUT, i.e., zero when
the DAC is at full scale and approximately 10 mA at zero input
code.
A relatively constant current (not code dependent) flows out the
REFERENCE COMMON (Pin 23).
The current flowing out of the VEE supply (Pin 22) comes from
a combination of reference ground and BIPOLAR OFFSET
(Pin 21). The plus and minus 15 V supplies are decoupled to
the REFERENCE COMMON.
The ground side of the load resistor RL, ANALOG COMMON
and LADDER COMMON should be tied together as close to
the package pins as possible. The analog output voltage is then
referred to this node and thus it becomes the “high quality”
ground for the AD568. The REFERENCE COMMON (and
Bipolar offset when not used), should also be connected to this
node.
All of the current that flows into the VTH terminal (Pin 13) from
the resistor tied to the 5 V logic supply (or other convenient
positive supply) flows out the THRESHOLD COMMON (Pin
14). This ground pin should be returned directly to the digital
ground plane on its own individual line.
The +5 V logic supply should be decoupled to the THRESH-
OLD COMMON.
Because the VTH pin is connected directly to the DAC switches
it should be decoupled to the analog output signal common.
In order to preserve proper operation of the DAC switches, the
digital and analog grounds need to eventually be tied together.
This connection between the ground planes should be made
within 1/2" of the DAC.
The Use of Ground and Power Planes
If used properly, ground planes can perform a myriad of func-
tions on high-speed circuit boards: bypassing, shielding, current
transport, etc. In mixed signal design, the analog and digital por-
tions of the board should be distinct from one another, with the
analog ground plane covering analog signal traces and the digital
ground plane confined to areas covering digital interconnect.
The two ground planes should be connected at or near the
DAC. Care should be taken to insure that the ground plane is
uninterrupted over crucial signal paths. On the digital side, this
includes the digital input lines running to the DAC and any
clock lines. On the analog side, this incudes the DAC output
signal as well as the supply feeders. The use of side runs or
planes in the routing of power lines is also recommended. This
serves the dual function of providing a low series impedance
power supply to the part as well as providing some ‘‘free’’ ca-
pacitive decoupling to the appropriate ground plane. Figure
18 illustrates many of the points discussed above. If more layers
of interconnect are available, even better results are possible.
Using the Right Bypass Capacitors
Probably the most important external components associated
with any high-speed design are the capacitors used to bypass
the power supplies. Both selection and placement of these ca-
pacitors can be critical and, to a large extent, dependent upon
the specifics of the system configurations. The dominant consid-
eration in selection of bypass capacitors for the AD568 is mini-
mization of series resistance and inductance. Many capacitors
will begin to look inductive at 20 MHz and above, the very fre-
quencies we are most interested in bypassing. Ceramic and film-
type capacitors generally feature lower series inductance than
tantalum or electrolytic types. A few general rules are of univer-
sal use when approaching the problem of bypassing:
Bypass capacitors should be installed on the printed circuit
board with the shortest possible leads consistent with reliable
construction. This helps to minimize series inductance in the
leads. Chip capacitors are optimal in this respect.
Some series inductance between the DAC supply pins and the
power supply plane often helps to filter out high-frequency
power supply noise. This inductance can be generated using a
small ferrite bead.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AD568K | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit Ultrahigh Speed Monolithic D/A Converter |
| AD568KQ | 功能描述:IC DAC 12BIT HS MONO 35NS 24CDIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時(shí)間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD568S | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit Ultrahigh Speed Monolithic D/A Converter |
| AD568SE/883B | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| AD568SQ | 功能描述:數(shù)模轉(zhuǎn)換器- DAC IC MONO 12-BIT D/A CONV RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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