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參數(shù)資料
| 型號： | AD568JQ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT HS MONO 35NS 24CDIP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1 |
| 設置時間： | 35ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-CDIP（0.300"，7.62mm） |
| 供應商設備封裝： | 24-CDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電流，單極；1 電流，雙極；1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | * |
AD568
REV. A
–12–
Circuit Details
Figure 20 shows an approximate timing budget for the A/D con-
verter. If 12 cycles are to be completed in 1
s, approximately
80 ns is allowed for each cycle. Since the Schottky diodes clamp
the voltage of the summing junction, the DAC settling time ap-
proaches the current-settling value of 35 ns, and hence uses up
less than half the timing budget.
To maintain simplicity, a simple clock is used that runs at a
constant rate throughout the conversion, with a duty cycle of
approximately 90%. If absolute speed is worth the additional
complexity, the clock frequency can be increased as the conver-
sion progresses since the DAC must settle from increasingly
smaller steps.
When seeking a cycle time of less than 100 ns, the delays gener-
ated by the older generation SAR registers become problematic.
Newer, high speed SAR logic chips are becoming available in
the classic 2504 pinout that cuts the logic overhead in half. One
example of this is Zyrel’s ZR2504.
Finding a comparator capable of keeping up with this DAC ar-
rangement is fairly difficult: it must respond to an overdrive of
250
V (1 LSB) in less than 25 ns. Since no inexpensive com-
parator exists with these specs, special arrangements must be
made. The LT106 comparator provides relatively quick re-
sponse, but requires at least 5 mV of overdrive to maintain this
speed. A discrete preamplifier may be used to amplify the sum-
ming junction voltage to sufficiently overdrive the comparator.
Care must be exercised in the layout of the preamp/comparator
block to avoid introducing comparator instability with the
preamp’s additional gain.
10ns
35ns
15ns
10ns
0
10ns
20ns
30ns
40ns
50ns
60ns
70ns
80ns
CLOCK
PULSE
START OF NEXT
CLOCK CYCLE
LATCH COMPARATOR
START OF
CLOCK CYCLE
SAR
DELAY
DAC SETTLING
PREAMP
DELAY
COMPARATOR
DELAY
Figure 20. Typical Clock Cycle for a 1
s SAR A/D
Converter
HIGH-SPEED MULTIPLYING DAC
A powerful use for the AD568 is found in multiplying applica-
tions, where the DAC controls the amplitude of a high-speed
signal. Specifically, using the AD568 as the control voltage
input signal for the AD539 60 MHz analog multiplier and
AD5539 wideband op amp, a high-speed multiplying DAC can
be built.
In the application shown in Figure 21, the AD568 is used in a
buffered voltage output mode to generate the input to the
AD539’s control channel. The speed of the AD568 allows
oversampling of the control signal waveform voltage, thereby
providing increased spectral purity of the amplitude envelope
that modulates the analog input channels.
The AD568 is configured in the unbuffered unipolar output
mode. The internal 200
load resistor creates the 0-1 V FS
output signal, which is buffered and amplified to a 0-3 V range
suitable for the control channel of the AD539.
A 500
input impedance exists at Pin 1, the input channel. To
provide a buffer for the 0-1 V output signal from the AD568
looking into the impedance and to achieve the full-scale range,
the AD841, high-speed, fast settling op amp is included. The
gain of 3 is achieved with a 2 k
resistor configured in follower
mode with a 1 k
pot and 500 resistor. A 20 k pot with
connections to Pins 3, 4 and 12 is provided for offset trim.
The AD539 can accept two separate input signals, each with a
nominal full-scale voltage range of
±2 V. Each signal can then
be simultaneously controlled by the AD568 signal at the com-
mon input channels, Pins 11 and 14, applied to the AD5539 in
a subtracting configuration, provide the voltage output signal:
VOUT =
D
4096
×
VY1 –VY 2
2V
(0
≤D ≤4095)
For applications where only a single channel is involved, chan-
nel 2, VY2, is tied to ground. This provides:
VOUT =
D
4096
×
VY1
2V
(0
≤D ≤4095)
Some AD539 circuit details: The control amplifier compensa-
tion capacitor for Pin 2, CC, must have a minimum value of
300 pF to provide circuit stability. For improved bandwidth and
feedthrough, the feedthrough capacitor between Pins 1 and 2
should be 5-20% of CC. A Schottky diode at Pin 2 can improve
recovery time from small negative values of VX. Lead lengths
along the path of the high-speed signal from AD568 should be
kept at a minimum.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD568K | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit Ultrahigh Speed Monolithic D/A Converter |
| AD568KQ | 功能描述:IC DAC 12BIT HS MONO 35NS 24CDIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1,000 系列:- 設置時間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD568S | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit Ultrahigh Speed Monolithic D/A Converter |
| AD568SE/883B | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| AD568SQ | 功能描述:數(shù)模轉換器- DAC IC MONO 12-BIT D/A CONV RoHS:否 制造商:Texas Instruments 轉換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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