參數(shù)資料
型號(hào)： AD6635
廠商： Analog Devices, Inc.
元件分類(lèi)： 基帶處理器
英文描述： 4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP)
中文描述： 4通道，80 MSPS的WCDMA的接收信號(hào)處理器（RSP）
文件頁(yè)數(shù)： 10/60頁(yè)
文件大?。?/td> 799K
代理商： AD6635
REV. 0
–10–
AD6635
MICROPROCESSOR PORT TIMING CHARACTERISTICS
1, 2
Test
Level
AD6635BB
Min
Parameter (Conditions)
Temp
Typ
Max
Unit
MICROPROCESSOR PORT, MODE MNM (MODE = 0)
MODE INM WRITE TIMING
t
SC
Control
3
to
≠
CLKn Setup Time
t
HC
Control
3
to
≠
CLKn Hold Time
t
HWR
WR(
RW) to RDY(
DTACK
) Hold Time
t
SAM
Address/Data to
WR
(RW) Setup Time
t
HAM
Address/Data to RDY(
DTACK
) Hold Time
t
DRDY
WR
(RW) to RDY(
DTACK
) Delay
t
ACC
WR
(RW) to RDY(
DTACK
) High Delay
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
2.0
2.5
7.0
3.0
5.0
8.0
4 t
CLK
ns
ns
ns
ns
ns
ns
ns
5 t
CLK
9 t
CLK
MODE INM READ TIMING
t
SC
Control
3
to
≠
CLKn Setup Time
t
HC
Control
3
to
≠
CLKn Hold Time
t
SAM
Address to
RD
(
DS
) Setup Time
t
HAM
Address to Data Hold Time
t
DRDY
RD
(
DS
) to RDY(
DTACK
) Delay
t
ACC
RD(DS
) to RDY(
DTACK
) High Delay
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
5.0
2.0
0.0
5.0
8.0
8 t
CLK
ns
ns
ns
ns
ns
ns
10 t
CLK
13 t
CLK
MICROPROCESSOR PORT, MODE MNM (MODE = 1)
MODE MNM WRITE TIMING
t
SC
Control
3
to
≠
CLKn Setup Time
t
HC
Control
3
to
≠
CLKn Hold Time
t
HDS
DS
(
RD
) to
DTACK
(RDY) Hold Time
t
HRW
RW(
WR
) to
DTACK
(RDY) Hold Time
t
SAM
Address/Data to RW(
WR
) Setup Time
t
HAM
Address/Data to RW(
WR
) Hold Time
t
DDTACK
DS
(
RD
) to
DTACK
(RDY) Delay
t
ACC
RW(
WR
) to
DTACK
(RDY) Low Delay
Full
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
IV
2.0
2.5
8.0
7.0
3.0
5.0
8.0
4 t
CLK
ns
ns
ns
ns
ns
ns
ns
ns
5 t
CLK
9 t
CLK
MODE MNM READ TIMING
t
SC
Control
3
to
≠
CLKn Setup Time
t
HC
Control
3
to
≠
CLKn Hold Time
t
HDS
DS
(
RD
) to
DTACK
(RDY) Hold Time
t
SAM
Address to
DS
(
RD
) Setup Time
t
HAM
Address to Data Hold Time
t
DDTACK
DS
(
RD
) to
DTACK
(RDY) Delay
t
ACC
DS
(
RD
) to
DTACK
(RDY) Low Delay
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
5.0
2.0
8.0
0.0
5.0
8.0
8 t
CLK
ns
ns
ns
ns
ns
ns
ns
10 t
CLK
13 t
CLK
NOTES
1
All Timing Specifications valid over VDD range of 2.25 V to 2.75 V, and VDDIO range of 3.0 V to 3.6 V.
2
C
LOAD
= 40 pF on all outputs unless otherwise specified.
3
Specification pertains to control signals: R/W, (
WR
),
DS
, (
RD
),
CS0
,
CS1
.
Specifications subject to change without notice.
相關(guān)PDF資料
PDF描述
AD6635BB 4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP)
AD6636 150 MSPS Wideband Digital Down-Converter (DDC)
AD6636BBCZ1 150 MSPS Wideband Digital Down-Converter (DDC)
AD6636BC 150 MSPS Wideband Digital Down-Converter (DDC)
AD6636CBCZ1 150 MSPS Wideband Digital Down-Converter (DDC)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD6635BB 功能描述:IC RSP 80MSPS QUAD 324-BGA RoHS:否 類(lèi)別:RF/IF 和 RFID >> RF 混頻器 系列:AD6635 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:100 系列:- RF 型:W-CDMA 頻率:2.11GHz ~ 2.17GHz 混頻器數(shù)目:1 增益:17dB 噪音數(shù)據(jù):2.2dB 次要屬性:- 電流 - 電源:11.7mA 電源電壓:2.7 V ~ 3.3 V 包裝:托盤(pán) 封裝/外殼:12-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:12-QFN-EP（3x3）
AD6635BB/PCB 制造商:Analog Devices 功能描述:Evaluation Kit For 4-Channel, 80MSPS WCDMA Receive Signal Processor
AD6635BBZ 制造商:Analog Devices 功能描述:Receive Signal Processor 324-Pin BGA
AD6636 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:150 MSPS Wideband Digital Down-Converter (DDC)
AD6636BBC 制造商:Analog Devices 功能描述:Digital Down Converter 256-Pin CSP-BGA
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