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參數(shù)資料
| 型號： | AD6635 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 基帶處理器 |
| 英文描述： | 4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP) |
| 中文描述： | 4通道，80 MSPS的WCDMA的接收信號處理器（RSP） |
| 文件頁數(shù)： | 41/60頁 |
| 文件大小： | 799K |
| 代理商： | AD6635 |
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REV. 0
AD6635
–41–
WAIT
ensures that the amount of time the AD6635 needs to
wait to begin data transmission is at least equal to the minimum
amount of time the TigerSHARC is expecting it to wait. If the
PCLK of the AD6635 is out of phase with the PCLK of the
TigerSHARC and the argument to the
ceil
( ) function is an
integer, then
WAIT
must be strictly greater than the value given
in the above formula. If the LCLKs are in phase, the maximum
output data rate is
f
f
LCLK
LCLK TSHARC
_
_
34
15
6
￡
￥
otherwise, it is
f
f
LCLK
LCLK TSHARC
_
_
34
14
6
￡
￥
TigerSHARC Configuration
Since the AD6635 is always the transmitter in this link and the
TigerSHARC is always the receiver, the following values can be
programmed into the LCTL register for the link port used to
receive AD6635 output data. “User” means that the actual
register value depends on the user’s application.
Table IX. TigerSHARC LCTLx Register Configuration
VERE
SPD
LTEN
PSIZE
TTOE
CERE
LREN
RTOE
0
User
0
1
0
0
1
1
Table X. Channel Memory Map (Part 1)
Channel Address
Register
Bit Width
Comments
00–7F
80
81
Coefficient Memory (CMEM)
CHANNEL SLEEP
Soft_Sync Control Register
20
1
2
128 20-Bit Memory
0: SLEEP Bit from EXT_ADDRESS 3
1: Hop
0: Start
2: First SYNC Only
1: Hop_En
0: Start_En
Start Holdoff Value
NCO_FREQ Holdoff Value
NCO_FREQ[15:0]
NCO_FREQ[31:16]
NCO_PHASE[15:0]
8–7: SYNC Input Select[1:0]
6: WB Input Select B/A
5–4: Input Enable Control
11: Clock on IEN Transition to Low
10: Clock on IEN Transition to High
01: Clock on IEN High
00: Mask on IEN Low
3: Clear Phase Accumulator on HOP
2: Amplitude Dither
1: Phase Dither
0: Bypass (A Input
I-Path, B
Q)
(C Input
I-
Path, D
Q)
82
Pin_SYNC Control Register
3
83
84
85
86
87
88
Start Holdoff Counter
NCO Frequency Holdoff Counter
NCO Frequency Register 0
NCO Frequency Register 1
NCO Phase Offset Register
NCO Control Register
16
16
16
16
16
9
89–8F
Unused
MEMORY MAP
This section describes the memory maps for channel, memory,
and for the input and output control registers.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD6635BB | 4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP) |
| AD6636 | 150 MSPS Wideband Digital Down-Converter (DDC) |
| AD6636BBCZ1 | 150 MSPS Wideband Digital Down-Converter (DDC) |
| AD6636BC | 150 MSPS Wideband Digital Down-Converter (DDC) |
| AD6636CBCZ1 | 150 MSPS Wideband Digital Down-Converter (DDC) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6635BB | 功能描述:IC RSP 80MSPS QUAD 324-BGA RoHS:否 類別:RF/IF 和 RFID >> RF 混頻器 系列:AD6635 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:100 系列:- RF 型:W-CDMA 頻率:2.11GHz ~ 2.17GHz 混頻器數(shù)目:1 增益:17dB 噪音數(shù)據(jù):2.2dB 次要屬性:- 電流 - 電源:11.7mA 電源電壓:2.7 V ~ 3.3 V 包裝:托盤 封裝/外殼:12-VFQFN 裸露焊盤 供應商設(shè)備封裝:12-QFN-EP（3x3） |
| AD6635BB/PCB | 制造商:Analog Devices 功能描述:Evaluation Kit For 4-Channel, 80MSPS WCDMA Receive Signal Processor |
| AD6635BBZ | 制造商:Analog Devices 功能描述:Receive Signal Processor 324-Pin BGA |
| AD6636 | 制造商:AD 制造商全稱:Analog Devices 功能描述:150 MSPS Wideband Digital Down-Converter (DDC) |
| AD6636BBC | 制造商:Analog Devices 功能描述:Digital Down Converter 256-Pin CSP-BGA |
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