參數(shù)資料
型號(hào)： AD6635
廠商： Analog Devices, Inc.
元件分類： 基帶處理器
英文描述： 4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP)
中文描述： 4通道，80 MSPS的WCDMA的接收信號(hào)處理器（RSP）
文件頁(yè)數(shù)： 55/60頁(yè)
文件大?。?/td> 799K
代理商： AD6635
REV. 0
AD6635
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in turn access the location pointed to by this address. The channel
address register cannot be read back while the broadcast bit
is set high.
SOFT_SYNC Control Register
External Address [5] is the SOFT_SYNC control register and is
write-only.
Bits 0–3 of this register are the SOFT_SYNC control bits.
These bits may be written to by the controller to initiate the
synchronization of a selected channel. The four SYNC bits go
to the channels indicated. Bit 0 to Channel 0, Bit 1 to Channel
1, Bit 2 to Channel 2, and Bit 3 to Channel 3 when
CS0
is
used. Similarly when
CS1
is used, Bit 0 to Channel 4, Bit 1 to
Channel 5, Bit 2 to Channel 6, and Bit 3 to Channel 7.
Bit 4 determines if the synchronization is to apply to a chip
start. If this bit is set, a chip start will be initiated by the SYNC.
Bit 5 determines if the synchronization is to apply to a chip hop.
If this bit is set, a SOFT SYNC is issued and the NCO fre-
quency will be updated after the frequency holdoff counter
counts down to zero.
Bit 6 configures the internal data bus. If this bit is set low, the
internal ADC data buses are configured normally. If this bit is
set, the internal test signals are selected. The internal test sig-
nals are configured in Bit 7 of this register.
Bit 7 if set clear, a negative full-scale signal is generated and made
available to the internal data bus. If this bit is high, the internal
pseudorandom sequence generator is enabled and this data is
available to the internal data bus. The combined functions of Bits
6 and 7 facilitate verification of a given filter design.
PIN_SYNC Control Register
External Address [4] is the PIN_SYNC control register and is
write-only.
Bits 0–3 of this register are the SYNC_EN control bits. These
bits may be written to by the controller to allow pin synchroni-
zation of a selected channel. Although there are four inputs,
these do not necessarily go to the channel of the same num-
ber. This is fully configurable at the channel level as to which
bit to look at. All four channels may be configured to syn-
chronize from a single position, or they may be paired, or all
independent. Unlike the Sync Pins, SYNC_EN are different for
Channels 0–3 and Channels 4–7.
Bit 4 determines if the synchronization is to apply to a chip
start. If this bit is set, a chip start will be initiated when the
PIN_SYNC occurs.
Bit 5 determines if the synchronization is to apply to a chip hop.
If this bit is set, a SOFT SYNC is issued and the NCO fre-
quency will be updated after the frequency holdoff counter
counts down to 0.
Bit 6 is used to ignore repetitive synchronization signals. In
some applications, this signal may occur periodically. If this bit
is clear, each PIN_SYNC will restart/hop the channel. If this bit
is set, only the first occurrence will cause the chip to take action.
Bit 7 is used with Bits 6 and 7 of external address 5. When this
bit is cleared, the data supplied to the internal data bus simu-
lates a normal ADC. When this bit is set, the data supplied is in
the form of a time-multiplexed ADC, such as the AD6600 (this
allows the equivalent of testing in the 4-channel input mode).
Internally, when set, this bit forces the IEN pin to toggle as if it
were driven by the A/B signal of the AD6600.
SLEEP Control Register
External Address [3] is the sleep register.
Bits 3–0 control the state of each of the channels. Each bit
corresponds to one of the possible RSP channels within the
device. If this bit is cleared, the channel operates normally.
However, when this bit is set, the indicated channel enters a low
power sleep mode.
Bit 4 is reserved and should always be set to 0.
Bit 5 allows access to the Input/Output Control Port registers.
When this bit is set low, the normal channel memory map is
accessed. However, when this bit is set high, it allows access to
the Input/Output Port Control registers. Access to these regis-
ters allows the lower and upper thresholds to be set along with
dwell time as well as the Half-band, AGC, and output port
(parallel /link) features to be configured. When this bit is set,
the value in external address 6 (CAR) points to the memory
map for the Input/Output Port Control registers instead of the
normal channel memory map.
Bits 6–7 are reserved and should be set low.
Data Address Registers
External Address [2–0] form the data registers DR2, DR1, and
DR0, respectively. All internal data-words have widths that are
less than or equal to 20 bits. Accesses to External Address 0
(i.e., DR0) triggers an internal access to the AD6635 based on
the address indicated in the ACR and CAR. Thus, during
writes to the internal registers, External Address 0 (DR0) must
be written last. At this point, data is transferred to the internal
memory indicated in A[9:0]. Reads are performed in the oppo-
site direction. Once the address is set, External Address 0
(DR0) must be the first data register read to initiate an internal
access. DR2 is only four bits wide. Data written to the upper
four bits of this register will be ignored. Likewise reading from
this register will produce only 4 LSBs.
Write Sequencing
Writing to an internal location is achieved by first writing the
upper two bits of the address to Bits 1–0 of the ACR. Bits 7–2
of the ACR may be set to select the required Broadcast mode as
indicated above. The CAR is then written with the lower eight
bits of the internal address (it doesn’t matter if the CAR is
written before the ACR, as long as both are written before the
internal access). The ACR needs to be written with the upper
two bits of address (indicating the channel used) only when
writing data to channel memory map. If input/output control
registers need to be written, Bit 5 of the SLEEP register should
be set and the upper two bits of the address in ACR will have
no effect.
Data register 2 (DR2) and register 1 (DR1) must be written
first, because the write to data register DR0 triggers the internal
access. Data register DR0 must always be the last register writ-
ten to initiate the internal write.
Read Sequencing
Reading from the microport is accomplished in the same manner.
The internal address is set up the same way as the write. A read
from data register DR0 activates the internal read, thus register
DR0 must always be read first to initiate an internal read, followed
by DR1 and DR2. This provides the 8 LSBs of the internal read
through the microport (D[7:0]). Additional data registers can
be read to read the balance of the internal memory.
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