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參數(shù)資料
| 型號(hào)： | AD6635 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 基帶處理器 |
| 英文描述： | 4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP) |
| 中文描述： | 4通道，80 MSPS的WCDMA的接收信號(hào)處理器（RSP） |
| 文件頁數(shù)： | 26/60頁 |
| 文件大小： | 799K |
| 代理商： | AD6635 |
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REV. 0
–26–
AD6635
IN13
IN2
IN1
IN0
IEN
D10 (MSB)
D0 (LSB)
AD6600
AD6635
EXP1
EXP0
RSSI1
RSSI0
EXP2
RSSI2
AB_OUT
Figure 28. Typical Interconnection of the AD6600
Gain-Ranging ADC and the AD6635.
NUMERICALLY CONTROLLED OSCILLATOR
Frequency Translation
This processing stage comprises a digital tuner consisting of two
multipliers and a 32-bit complex NCO. Each channel of the
AD6635 has an independent NCO. The NCO serves as a quadra-
ture local oscillator capable of producing an NCO frequency
between –CLK/2 and +CLK/2 with a resolution of CLK/2
32
in the
complex mode. The worst-case spurious signal from the NCO is
better than –100 dBc for all output frequencies.
The NCO frequency value in registers 0x85 and 0x86 are inter-
preted as a 32-bit unsigned integer. The NCO frequency is
calculated using the equation below.
NCO FREQ
_
f
CLKn
CHANNEL
mod
,
=
￥
ê
ˉ
2
1
32
where
NCO_FREQ
is the 32-bit integer (registers 0x85 and
0x86) that the user needs to set in order to tune to a desired
frequency
f
CHANNEL
, and
CLKn
is the AD6635 master clock rate
or Input data rate, depending on the Input Enable mode used.
See the Input Enable Control section to determine when it is
CLK and when it is Input data rate. For Channels 0 through 3
use CLK0, and for Channels 4 through 7 use CLK1.
“mod” is similar to the remainder function. For example if
f
CHANNEL
= 220 MHz and CLK = 80 MHz, then mod(220/80,1)
= mod(2.75,1) = 0.75.
But for negative frequencies, for example,
mod(–220/80,1) = mod(–1.75,1) = 0.25.
This definition works if
NCO_FREQ
register is treated as a
signed number.
NCO Frequency Holdoff Register
When the NCO frequency registers are written, data is actually
passed to a shadow register. Data may be moved to the main
registers by one of two methods: when the channel comes out of
sleep mode, or when a SYNC hop occurs. In either event, a
counter can be loaded with the NCO Frequency Holdoff regis-
ter value. The 16-bit unsigned integer counter (0x84) starts
counting down, clocked by the Master clock, and when it reaches
zero, the new frequency value in the shadow register is written
to the NCO frequency register. The NCO could also be set up
to SYNC immediately, in which case the Frequency Holdoff
counter is bypassed (by writing a value of 1) and new frequency
values are updated immediately. If a zero is written, then SYNC
will never occur.
Phase Offset
The Phase Offset register (0x87) adds an offset to the phase
accumulator of the NCO. The NCO phase accumulator starts
with the value in this register in the event of a START SYNC.
This is a 16-bit register and is interpreted as a 16-bit unsigned
integer. A 0x0000 in this register corresponds to a 0 radian
offset, and a 0xFFFF corresponds to an offset of 2
￥
(1 – 1/(2
16
))
radians. This register allows multiple NCOs to be synchronized to
produce sine waves with a known and steady phase difference.
NCO Control Register
The NCO control register located at 0x88 is used to configure
the features of the NCO. These are controlled on a per channel
basis and are described below.
Bypass
The NCO in the front end of the AD6635 can be bypassed.
Bypass mode is enabled by setting Bit 0 of 0x88 high. When the
NCO is bypassed, down conversion is not performed and the
AD6635 channel functions simply as a real filter on complex
data. This is useful for a baseband sampling application where
the A input is connected to the I signal path within the filter,
and the B input is connected to the Q signal path for Channels 0
through 3. Similarly, input C is connected to I signal path and
input D to Q signal path for Channels 4 through 7. This may be
desired if the digitized signal has already been converted to
baseband in prior analog stages or by other digital preprocessing.
Phase Dither
The AD6635 provides a phase dither option for improving the
spurious performance of the NCO. Phase dither is enabled by
setting Bit 1 of the NCO control register. When phase dither is
enabled by setting this bit high, spurs due to phase truncation in
the NCO are randomized. The energy from these spurs is
spread into the noise floor and spurious-free dynamic range is
increased at the expense of very slight decreases in the SNR.
The choice of whether phase dither is used in a system will
ultimately be decided by the system goals. If lower spurs are
desired at the expense of a slightly raised noise floor, it should
be employed. If a low noise floor is desired and the higher spurs
can be tolerated or filtered by subsequent stages, phase dither is
not needed.
Amplitude Dither
Amplitude dither can also be used to improve spurious perfor-
mance of the NCO. Amplitude dither is enabled by setting Bit 2.
Amplitude dither improves performance by randomizing the
amplitude quantization errors within the angular-to-Cartesian
conversion of the NCO. This option may reduce spurs at the
expense of a slightly raised noise floor. Amplitude dither and phase
dither can be used together, separately, or not at all.
Clear Phase Accumulator on Hop
When Bit 3 is set, the NCO phase accumulator is cleared prior
to a frequency hop. This ensures a consistent phase of the NCO
on each hop. The NCO phase offset is unaffected by this setting
and is still in effect. If phase-continuous hopping is desired, this
bit should be cleared and the last phase in the NCO phase regis-
ter will be the initiating point for the new frequency.
Input Enable Control
There are four different modes of operation for the input enable.
Each of the high speed input ports includes an IEN line. Any of
the four filter Channels 0 through 3 can be programmed to take
data from either of the two Input Ports A or B (see the WB
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| AD6635BB | 功能描述:IC RSP 80MSPS QUAD 324-BGA RoHS:否 類別:RF/IF 和 RFID >> RF 混頻器 系列:AD6635 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:100 系列:- RF 型:W-CDMA 頻率:2.11GHz ~ 2.17GHz 混頻器數(shù)目:1 增益:17dB 噪音數(shù)據(jù):2.2dB 次要屬性:- 電流 - 電源:11.7mA 電源電壓:2.7 V ~ 3.3 V 包裝:托盤 封裝/外殼:12-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:12-QFN-EP（3x3） |
| AD6635BB/PCB | 制造商:Analog Devices 功能描述:Evaluation Kit For 4-Channel, 80MSPS WCDMA Receive Signal Processor |
| AD6635BBZ | 制造商:Analog Devices 功能描述:Receive Signal Processor 324-Pin BGA |
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| AD6636BBC | 制造商:Analog Devices 功能描述:Digital Down Converter 256-Pin CSP-BGA |
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