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參數(shù)資料
| 型號(hào)： | AD6635 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 基帶處理器 |
| 英文描述： | 4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP) |
| 中文描述： | 4通道，80 MSPS的WCDMA的接收信號(hào)處理器（RSP） |
| 文件頁數(shù)： | 27/60頁 |
| 文件大小： | 799K |
| 代理商： | AD6635 |
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REV. 0
AD6635
–27–
Input Select section). Similarly, any of the four filter Channels
4 through 7 can be programmed to take data from either of the
two Input Ports C or D. Along with data is the IENx signal. Each
filter channel can be configured to process the IEN signal in one
of four modes. Three of the modes are associated with when
data is processed based on a time division multiplexed data
stream. The fourth mode is used in applications that employ time
division duplex, such as radar, sonar, ultrasound, and com-
munications that involve TDD.
Mode 00: Blank on IEN Low
In this mode, data is blanked while the IEN line is low. While
the IEN line is high, new data is strobed on each rising edge of
the input clock. When the IEN line is lowered, input data is
replaced with zero values. During this period, the NCO contin-
ues to run such that when the IEN line is raised again, the
NCO value will be at the same value it would have been had the
IEN line never been lowered. This mode has the effect of blank-
ing the digital inputs when the IEN line is lowered. Back end
processing (rCIC2, CIC5, and RCF) continues while the IEN
line is high. This mode is useful for time division multiplexed
applications.
Mode 01: Clock on IEN High
In this mode, data is clocked into the chip while the IEN line is
high. While the IEN line is high, new data is strobed on each
rising edge of the input clock. When the IEN line is lowered,
input data is no longer latched into the channel. Additionally,
NCO advances are halted. However, back end processing
(rCIC2, CIC5, and RCF) continues during this period. The
primary use for this mode is to allow for a clock that is faster
than the input sample data rate so that more filter taps can be
computed than would otherwise be possible. In the diagram
below, input data is strobed only while IEN is high, despite the
fact that the CLK continues to run at a rate four times faster
than the data.
n + 1
n
IN[13:0]
E[2:0]
CLK
IEN
t
SI
t
HI
Figure 29. Fractional Rate Input Timing (4
￥
CLK)
in Mode 01
Mode 10: Clock on IEN Transition to High
In this mode, data is clocked into the chip only on the first
clock edge after the rising transition of the IEN line. Although
data is only latched on the first valid clock edge, the back end
processing (rCIC2, CIC5, and RCF) continues on each avail-
able clock that may be present, similar to Mode 01. The NCO
phase accumulator is incremented only once for each new input
data sample, not once for each input clock.
Mode 11: Clock on IEN Transition to Low
In this mode, data is clocked into the chip only on the first clock
edge after the falling transition of the IEN line. Although data is
only latched on the first valid clock edge, the back end process-
ing (rCIC2, CIC5, and RCF) continues on each available clock
that may be present, similar to Mode 01. The NCO phase accu-
mulator is incremented only once for each new input data sample,
not once for each input clock.
WB Input Select
Bit 6 in this register controls which input port is selected for
signal processing. For Channels 0 through 3, if this bit is set
high, then Input Port B (INB, EXPB, and IENB) is connected
to the selected AD6635 channel. If this bit is cleared, Input Port A
(INA, EXPA, and IENA) is connected to the selected filter
channel. Similarly for Channels 4 through 7 Input Port D is
selected when Bit 6 is set and Input Port C is selected when this
bit is cleared.
Sync Select
Bits 7 and 8 of this register determine which external sync pin is
associated with the selected channel. The AD6635 has four sync
pins named SYNCA, SYNCB, SYNCC, and SYNCD. Any of
these sync pins can be associated with any of the eight receiver
channels within the AD6635. Additionally, if only one sync
signal is required for the system, all eight receiver channels can
reference the same sync pin. Bit value 00 selects SYNCA, 01
selects SYNCB, 10 selects SYNCC, and 11 selects SYNCD.
SECOND-ORDER rCIC FILTER
The rCIC2 filter is a second-order resampling Cascaded Inte-
grator Comb filter. The resampler is implemented using a
unique technique that does not require the use of a high speed
clock, thus simplifying the design and saving power. The
resampler allows noninteger relationships between the master
clock and the output data rate. This allows easier implementa-
tion of systems that are either multimode or require a master
clock that is not a multiple of the data rate to be used.
Interpolation up to 512 and decimation up to 4096 is allowed in
the rCIC2. The resampling factor for the rCIC2 (
L
) is a 9-bit
integer. When combined with the 12-bit decimation factor
M
,
the total rate change can be any fraction in the form of:
R
L
M
1
R
rCIC
rCIC
2
2
=
￡
The only constraint is that the ratio
L/M
must be less than or
equal to 1. This implies that the rCIC2 decimates by 1 or more.
Resampling is implemented by apparently increasing the input
sample rate by the factor
L
using zero stuffing for the new data
samples. Following the resampler is a second-order cascaded
integrator comb filter. Filter characteristics are determined only
by the fractional rate change (
L/M
).
The filter can process signals at the full rate of the input port
80 MHz. The output rate of this stage is given by the equa-
tion below.
f
L
f
M
SAMP
rCIC
SAMP
rCIC
2
2
=
2
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| AD6635BB | 4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP) |
| AD6636 | 150 MSPS Wideband Digital Down-Converter (DDC) |
| AD6636BBCZ1 | 150 MSPS Wideband Digital Down-Converter (DDC) |
| AD6636BC | 150 MSPS Wideband Digital Down-Converter (DDC) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AD6635BB | 功能描述:IC RSP 80MSPS QUAD 324-BGA RoHS:否 類別:RF/IF 和 RFID >> RF 混頻器 系列:AD6635 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:100 系列:- RF 型:W-CDMA 頻率:2.11GHz ~ 2.17GHz 混頻器數(shù)目:1 增益:17dB 噪音數(shù)據(jù):2.2dB 次要屬性:- 電流 - 電源:11.7mA 電源電壓:2.7 V ~ 3.3 V 包裝:托盤 封裝/外殼:12-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:12-QFN-EP（3x3） |
| AD6635BB/PCB | 制造商:Analog Devices 功能描述:Evaluation Kit For 4-Channel, 80MSPS WCDMA Receive Signal Processor |
| AD6635BBZ | 制造商:Analog Devices 功能描述:Receive Signal Processor 324-Pin BGA |
| AD6636 | 制造商:AD 制造商全稱:Analog Devices 功能描述:150 MSPS Wideband Digital Down-Converter (DDC) |
| AD6636BBC | 制造商:Analog Devices 功能描述:Digital Down Converter 256-Pin CSP-BGA |
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