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參數(shù)資料
| 型號： | AD6635 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 基帶處理器 |
| 英文描述： | 4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP) |
| 中文描述： | 4通道，80 MSPS的WCDMA的接收信號處理器（RSP） |
| 文件頁數(shù)： | 56/60頁 |
| 文件大?。?/td> | 799K |
| 代理商： | AD6635 |
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REV. 0
–56–
AD6635
Read/Write Chaining
The microport of the AD6635 allows for multiple accesses while
CS
n is held low. The user can access multiple locations by
pulsing the
WR
or
RD
line and changing the contents of the
external 3-bit address bus. External access to the external regis-
ters of Table XVI is accomplished in one of two modes using
the
CS0
,
CS1
,
RD
,
WR
, and MODE inputs. The access modes
are Intel nonmultiplexed mode and Motorola nonmultiplexed
mode. These modes are controlled by the MODE input
(MODE = 0 for INM, MODE = 1 for MNM).
CS0
,
CS1
,
RD
,
and
WR
control the access type for each mode.
Intel Nonmultiplexed Mode (INM)
MODE must be tied low to operate the AD6635 microproces-
sor in INM mode. The access type is controlled by the user with
the
CS0
,
CS1
,
RD
(
DS
), and
WR
(RW) inputs. The RDY
(
DTACK
) signal is produced by the microport to communicate
to the user that an access has been completed. RDY (
DTACK
)
goes low at the start of the access and is released when the inter-
nal access cycle is complete. See the timing diagrams for both
the read and write modes in the Specifications.
Motorola Nonmultiplexed Mode (MNM)
MODE must be tied high to operate the AD6635 microprocessor
in MNM mode. The access type is controlled by the user with
the
CS0
,
CS1
,
DS
(
RD
), and RW (
WR
) inputs. The
DTACK
(RDY) signal is produced by the microport to communicate to
the user that an access has been completed.
DTACK
(RDY)
goes low when an internal access is complete and then will
return high after
DS
(
RD
) is de-asserted. See the timing diagrams
for both the read and write modes in the Specifications.
SERIAL PORT CONTROL
The AD6635 has a two serial ports serving as a control inter-
face apart from the microport control interface. The serial port
input pin (SDI0) can access all of the internal registers for
Channels 0–3, control registers for Input/Output Ports A and
B, Half-band/AGCs A and B, and has preemptive access over
the microport. Similarly SDI4 can access all of the internal
registers for Channels 4–7, Input/Output Ports C and D, Half-
band/AGCs C and D, and has preemptive access over the
microport. In this manner, a single DSP could be used to
control the AD6635 over the serial port control interface.
The serial control port uses the serial clock (SCLK0 and SCLK4).
The serial input port is self-framing as described below, and
allows more efficient use of the serial input bandwidth for pro-
gramming. The beginning of a serial input frame is signaled by
a frame bit that appears on the SDI pin. This is the MSB of the
serial input frame. After the frame bit has been sampled high on
the falling edge of SCLK, a state counter will start and enable
an 11-bit serial shifter four serial clock cycles later. These four
SCLK cycles represent the “Don’t Care” bits of the serial frame
that are ignored. After all of the bits are shifted, the serial input
port will pass along the 8-bit data and 3-bit address to the arbi-
tration block. This 8-bit data and 3-bit address set programs the
external memory explained in the Microport Control section.
Hence, serial port programming is similar to microport
programming.
The serial word structure for the SDI input is illustrated in
Figure 45. Only 15 bits are listed so that the second bit in a
standard 16-bit serial word is considered the frame bit. The
shifting order begins with frame and shifts the address, MSB
first, and then the data, MSB first.
Effectively, SDI0 and SCLK0 can program every register that
can otherwise be programmed using
CS0
on the microport.
Similarly SDI4 and SCLK4 can program every register that can
otherwise be programmed using
CS1
on the microport.
Serial Port Timing Specifications
The AD6635 serial control channel can operate only in the slave
mode (SCLK should be supplied by the programming device).
The diagrams below indicate the required timing for each of the
specification.
SCLKn
t
SCLK
t
SCLKH
t
SCLKL
Figure 43. SCLKn (n = 0, 4) Timing Requirements
t
SSI
SCLKn
SDIn
DATA
t
HSI
Figure 44. Serial Input Data Timing
Requirements, n = 0, 4
SDI0, SDI4
SDI is the serial data input. Serial data is sampled on the falling
edge of SCLK. This pin is used in the serial control mode to
write the internal control registers of the AD6635.
SCLK0, SCLK4
SCLK is a clock input, and the SDI input is sampled on the
falling edge of SCLK, and all outputs are switched on the rising
edge of SCLK. The maximum speed of this port is 65 MHz.
Bits 5–4 determine how the sample clock for the channel is
derived from the high speed CLK signal. There are four possible
choices. Each is defined below; for further detail the Numerically
Controlled Oscillator (NCO) section.
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PDF描述 |
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| AD6635BB | 4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP) |
| AD6636 | 150 MSPS Wideband Digital Down-Converter (DDC) |
| AD6636BBCZ1 | 150 MSPS Wideband Digital Down-Converter (DDC) |
| AD6636BC | 150 MSPS Wideband Digital Down-Converter (DDC) |
| AD6636CBCZ1 | 150 MSPS Wideband Digital Down-Converter (DDC) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6635BB | 功能描述:IC RSP 80MSPS QUAD 324-BGA RoHS:否 類別:RF/IF 和 RFID >> RF 混頻器 系列:AD6635 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:100 系列:- RF 型:W-CDMA 頻率:2.11GHz ~ 2.17GHz 混頻器數(shù)目:1 增益:17dB 噪音數(shù)據(jù):2.2dB 次要屬性:- 電流 - 電源:11.7mA 電源電壓:2.7 V ~ 3.3 V 包裝:托盤 封裝/外殼:12-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:12-QFN-EP（3x3） |
| AD6635BB/PCB | 制造商:Analog Devices 功能描述:Evaluation Kit For 4-Channel, 80MSPS WCDMA Receive Signal Processor |
| AD6635BBZ | 制造商:Analog Devices 功能描述:Receive Signal Processor 324-Pin BGA |
| AD6636 | 制造商:AD 制造商全稱:Analog Devices 功能描述:150 MSPS Wideband Digital Down-Converter (DDC) |
| AD6636BBC | 制造商:Analog Devices 功能描述:Digital Down Converter 256-Pin CSP-BGA |
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