參數(shù)資料
型號(hào)： AD9259ABCPZRL7-50
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 20/52頁(yè)
文件大?。?/td> 0K
描述： IC ADC 14BIT SRL 50MSPS 48LFCSP
標(biāo)準(zhǔn)包裝： 750
位數(shù)： 14
采樣率（每秒）： 50M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 409mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 8 個(gè)單端，單極；4 個(gè)差分，單極
Data Sheet
AD9259
Rev. E | Page 27 of 52
SCLK/DTP Pin
The SCLK/DTP pin is for use in applications that do not require
SPI mode operation. This pin can enable a single digital test
pattern if it and the CSB pin are held high during device power-
up. When SCLK/DTP is tied to AVDD, the ADC channel
outputs shift out the following pattern: 10 0000 0000 0000. The
FCO and DCO function normally while all channels shift out the
repeatable test pattern. This pattern allows the user to perform
timing alignment adjustments among the FCO, DCO, and output
data. For normal operation, this pin should be tied to AGND
through a 10 k resistor. This pin is both 1.8 V and 3.3 V tolerant.
Table 12. Digital Test Pattern Pin Settings
Selected DTP
DTP Voltage
Resulting
D + x and D x
Resulting
FCO and DCO
Normal
Operation
10 k to AGND
Normal
operation
Normal operation
DTP
AVDD
10 0000 0000
0000
Normal operation
Additional and custom test patterns can also be observed when
commanded from the SPI port. Consult the Memory Map
section for information about the options available.
CSB Pin
The CSB pin should be tied to AVDD for applications that do
not require SPI mode operation. By tying CSB high, all SCLK
and SDIO information is ignored. This pin is both 1.8 V and
3.3 V tolerant.
RBIAS Pin
To set the internal core bias current of the ADC, place a resistor
(nominally equal to 10.0 k) to ground at the RBIAS pin. The
resistor current is derived on-chip and sets the AVDD current of
the ADC to a nominal 185 mA at 50 MSPS. Therefore, it is
imperative that at least a 1% tolerance on this resistor be used to
achieve consistent performance.
Voltage Reference
A stable, accurate 0.5 V voltage reference is built into the
AD9259. This is gained up internally by a factor of 2, setting
VREF to 1.0 V, which results in a full-scale differential input span
of 2 V p-p. The VREF is set internally by default; however, the
VREF pin can be driven externally with a 1.0 V reference to
improve accuracy.
When applying the decoupling capacitors to the VREF, REFT,
and REFB pins, use ceramic low ESR capacitors. These capacitors
should be close to the ADC pins and on the same layer of the
PCB as the AD9259. The recommended capacitor values and
configurations for the AD9259 reference pin are shown in
Table 13. Reference Settings
Selected Mode
SENSE Voltage
Resulting VREF (V)
Resulting
Differential
Span (V p-p)
External
Reference
AVDD
N/A
2 × external
reference
Internal,
2 V p-p FSR
AGND to 0.2 V
1.0
2.0
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