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參數(shù)資料
| 型號(hào)： | AD9259ABCPZRL7-50 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 49/52頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT SRL 50MSPS 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 50M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 功率耗散（最大）： | 409mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個(gè)單端，單極；4 個(gè)差分，單極 |
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AD9259
Data Sheet
Rev. E | Page 6 of 52
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = 0.5 dBFS, unless otherwise noted.
Table 3.
Temperature
Min
Typ
Max
Unit
CLOCK INPUTS (CLK+, CLK)
Logic Compliance
CMOS/LVDS/LVPECL
Differential Input Voltage2
Full
250
mV p-p
Input Common-Mode Voltage
Full
1.2
V
Input Resistance (Differential)
25°C
20
k
Input Capacitance
25°C
1.5
pF
LOGIC INPUTS (PDWN, SCLK/DTP)
Logic 1 Voltage
Full
1.2
3.6
V
Logic 0 Voltage
Full
0.3
V
Input Resistance
25°C
30
k
Input Capacitance
25°C
0.5
pF
LOGIC INPUT (CSB)
Logic 1 Voltage
Full
1.2
3.6
V
Logic 0 Voltage
Full
0.3
V
Input Resistance
25°C
70
k
Input Capacitance
25°C
0.5
pF
LOGIC INPUT (SDIO/ODM)
Logic 1 Voltage
Full
1.2
DRVDD + 0.3
V
Logic 0 Voltage
Full
0
0.3
V
Input Resistance
25°C
30
k
Input Capacitance
25°C
2
pF
LOGIC OUTPUT (SDIO/ODM)3
Logic 1 Voltage (IOH = 800 μA)
Full
1.79
V
Logic 0 Voltage (IOL = 50 μA)
Full
0.05
V
DIGITAL OUTPUTS (D + x, D x), (ANSI-644)
Logic Compliance
LVDS
Differential Output Voltage (VOD)
Full
247
454
mV
Output Offset Voltage (VOS)
Full
1.125
1.375
V
Output Coding (Default)
Offset binary
DIGITAL OUTPUTS (D + x, D x),
(Low Power, Reduced Signal Option)
Logic Compliance
LVDS
Differential Output Voltage (VOD)
Full
150
250
mV
Output Offset Voltage (VOS)
Full
1.10
1.30
V
Output Coding (Default)
Offset binary
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, at www.analog.com for definitions and for details on how these tests were
completed.
2
This is specified for LVDS and LVPECL only.
3
This is specified for 13 SDIO pins sharing the same connection.
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