參數(shù)資料
型號(hào): AD9259ABCPZRL7-50
廠商: Analog Devices Inc
文件頁數(shù): 33/52頁
文件大小: 0K
描述: IC ADC 14BIT SRL 50MSPS 48LFCSP
標(biāo)準(zhǔn)包裝: 750
位數(shù): 14
采樣率(每秒): 50M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 4
功率耗散(最大): 409mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 48-LFCSP-VQ(7x7)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 8 個(gè)單端,單極;4 個(gè)差分,單極
Data Sheet
AD9259
Rev. E | Page 39 of 52
CS
B
C2
17
0.
1
F
C2
20
0.
1
F
C2
21
0.
1
F
C
218
0.
1
F
C2
19
0.
1
F
C
223
0.
1
F
C2
22
0.
1
F
AV
DD
_3
.3
V
CL
K
CL
K
B
GND
GN
D
_P
A
D
OU
T0
OU
T0
B
OU
T1
OU
T1
B
RSET
S0
S1
S10
S2
S3
S4
S5
S6
S7
S8
S9
SY
N
C
B
VREF
VS
S
IG
N
A
L
=
DN
C;27
,2
8
IN
P
U
T
EN
C
O
D
E
EN
C
EN
C
DN
P
CL
O
C
K
CI
RC
UI
T
O
P
T
IO
NAL
C
L
O
C
K
DR
IV
E
CI
RCU
IT
DI
SAB
L
E
N
ABL
E
OP
T
ION
A
L
C
L
OC
K
OS
C
ILLA
TOR
C2
24
0.
1
F
R2
14
10
k
R2
15
10
k
14
7
8
1
3
5
12
10
OS
C
20
1
VF
A
C
3H
-L
C20
7
0.
1
F
DN
P
C2
08
0.
1
F
DN
P
C2
09
0.
1
F
DN
P
C2
15
0.
1
F
DNP
C2
11
0.
1
F
C2
10
0.
1
F
E
202
1
E
201
P
201
P
203
AVDD
_3.
3V
12
6
7
25
8
16
9
15
10
14
11
13
18
19
23
22
32
1
31
33
U2
02
S
IG
N
A
L
=
AV
DD
_3
.3
V
;
4,
17
,2
0,
2
1,
2
4,
26
,
29
,3
0
A
D
95
15
3
2
1
CR
20
1
HS
M
S
2812
R2
20
DNP
R2
40
24
3
R2
43
100
R24
1
243
R
242
10
0
6
5
4
3
2
1
T2
01
1
2
J20
5
C2
05
0.
1
F
C2
16
0.
1
F
R2
13
49.
9k
R2
16
0
R
221
10
k
R2
12
0 DN
P
R2
19
DN
P
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S1
0
OPT
_C
L
K
OPT
_C
L
K
CL
K
AV
D
_3.
3V
OP
T
_C
L
K
OP
T_
C
L
K
CL
K
CL
K
LV
P
E
C
L
OU
TP
U
T
LV
D
S
O
U
TP
U
T
CL
K
AV
DD
_3
.3
V
1
E
203
AV
DD
_3
.3
V
VCC
GN
D
OU
T
OE
OE'
GN
D
'
VCC
'
OU
T'
R2
44
DN
P
R
245 0
S4
S0
S5
S3
S2
S1
AV
D
D_
3.
3V
AV
D
D_
3.
3V
AV
D
D_
3.
3V
AV
D
D_
3.
3V
AV
D
D_
3.
3V
AV
D
D_
3.
3V
R2
46
DN
P
R2
47
0
R2
48
DN
P
R2
49
0
R2
50
DN
P
R2
51
0
R2
52
DN
P
R2
53
0
R2
54
DN
P
R2
55
0
R25
6
DN
P
R2
57
0
S1
0
S6
S9
S8
S7
AVDD
_3.
3V
AVDD
_3.
3V
AVDD
_3.
3V
AVDD
_3.
3V
AVDD
_3.
3V
R25
8
DN
P
R2
59
0
R26
0
DN
P
R2
61
0
R26
2
DN
P
R2
63
0
R26
4
DN
P
R2
65
0
A1
A2
A3
A4
A5
A6
A7
A8
A9
GN
D
A
B
1
G
ND
AB1
0
GN
D
A
B
2
GN
D
A
B
3
GN
D
A
B
4
GN
D
A
B
5
GN
D
A
B
6
GN
D
A
B
7
GN
D
A
B
8
GN
D
A
B
9
GN
D
C
D
1
G
N
DC
D1
0
GN
D
C
D
2
GN
D
C
D
3
GN
D
C
D
4
GN
D
C
D
5
GN
D
C
D
6
GN
D
C
D
7
GN
D
C
D
8
GN
D
C
D
9
H
E
A
D
ER
64
69
169
-1
R2
05
T
O
R2
11
OP
T
ION
A
L
O
U
TP
U
T
E
RM
IN
AT
IO
NS
D
IGITA
L
OU
TP
U
T
S
CS
B3
__
CHB
SD
I_
C
H
B
SDO
_CH
A
C
S
B
2_C
HA
C
S
B
1_C
HA
SDI
_CH
A
SCL
K
_C
HA
R20
6
DN
P
R21
1
DN
P
R21
0
DN
P
R20
9
DN
P
R20
8
DN
P
P2
02
R20
7
DN
P
SC
L
K
_C
H
B
DC
O
C1
0
C9
C8
C7
C6
C5
C4
C3
C2
C1
0
50
49
48
47
46
45
44
43
42
41
20
19
18
17
16
15
14
13
12
D1
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
B1
0
B9
B8
B7
B6
B5
B4
B3
B2
B1
11
CH
D
CH
C
CH
B
CH
A
FC
O
DC
O
CH
D
CH
C
CH
B
CH
A
FC
O
SD
O
_C
H
B
CS
B4
_CH
B
40
60
1
9
21
22
4
5
25
6
26
8
31
32
33
34
35
36
37
38
29
10
30
2
23
3
24
28
51
52
53
54
55
56
57
58
39
59
7
27
O
DM
E
N
ABL
E
CL
K
AVDD
CL
K
+
CL
K
D+
A
D+
B
D+
C
D+
D
D–
A
D–
B
D–
C
D–
D
DCO
+
DCO
DR
V
D
DR
G
N
D
FCO
+
FCO
PD
W
N
RBIA
S
REF
B
REF
T
S
C
LK
/D
TP
SD
IO
/O
D
M
SEN
SE
VI
N
+
A
VIN
+B
VIN
+C
VI
N
+
D
VIN
A
VIN
–B
VIN
–C
VI
N
D
VREF
AVDD
AV
DD
AV
DD
AV
DD
AV
DD
AVDD
DR
G
N
D
DR
V
D
REF
E
RENC
E
DECO
U
P
L
ING
C2
04
0.
1
F
C
203
0.
1
F
C20
2
2.
2
F
C2
01
0.
1
F
R205
10k
R203
100k
R204
100k
3
2
1
J2
01
1
8
73
0
20
18
16
14
19
17
15
13
24
23
11
12
22
21
10
2
25
26
27
32
35
36
39
45
46
5
6
9
31
40
43
44
28
29
41
33
38
47
4
34
37
48
3
42
U
201
A
D
9259
L
F
C
S
P
R2
02
100
k
C
S
B_
DU
T
1
2
3
J2
02
SD
IO
_O
D
M
1
2
3
J2
03
S
C
L
K
_D
T
P
3
2
1
J2
04
D
R
V
D
_D
U
T
D
R
V
D
_D
U
T
R
20
1
10
k
AVDD
_DUT
CHA
CHB
CHC
CHD
CHA
CHB
CHC
DCO
FCO
A
V
D
_D
U
T
A
V
D
_D
U
T
A
V
D
_D
U
T
AVDD
_DUT
AVDD
_DUT
VSEN
SE_D
UT
V
IN
_A
VIN
_B
VIN
_C
V
IN
_A
VIN_B
VREF_
DU
T
A
V
D
_D
U
T
A
V
D
_D
U
T
C
L
K
CHD
A
V
D
_D
U
T
A
V
D
_D
U
T
A
V
D
_D
U
T
A
V
D
_D
U
T
A
V
D
_D
U
T
V
IN
_D
VIN_C
V
IN
_D
G
N
D
G
N
D
A
V
D
_D
U
T
P
W
D
N
E
N
A
B
L
E
A
L
W
A
Y
S
E
N
A
B
L
E
S
P
I
D
T
P
E
N
A
B
L
E
U
20
3
CW
V
R
E
F
=
1V
V
R
E
F
=
E
X
T
E
R
N
A
L
V
R
E
F
=
0.
5V
R
E
M
O
V
E
C
21
4
W
H
E
N
U
S
IN
G
E
X
T
E
R
N
A
L
V
R
E
F
V
R
E
F
=
0.
5V
(1
+
R
23
2/
R
23
3)
V
R
E
F
S
E
L
E
C
T
R
E
F
E
R
E
N
C
E
C
IR
C
U
IT
C
21
2
0.
1
F
R
22
9
4.
99
k
C
21
4
1
F
C
21
3
0.
1
F
R
23
0
10
k
R
23
1
D
N
P
D
N
P
V
S
E
N
S
E
_D
U
T
R
22
8
47
0k
D
N
P
D
N
P
R
23
4
D
N
P
R
23
5
D
N
P
R
23
6
D
N
P
R
23
7
0
D
N
P
A
V
D
_D
U
T
V
R
E
F
_D
U
T
AVDD_DUT
T
R
IM
/N
C
V–
V
+
A
D
R
51
0
1V
R
23
2
D
N
P
R
23
3
D
N
P
R
21
7
0
R
21
8
0
R
22
5
0 DN
P
R
22
6
49
.9
D
N
P
R
22
7
0 DN
P
R
23
8
D
N
P
R
23
9
10
k
C
20
6
0.
1
F
R
22
3
0
R
22
4
0
R
22
2
4.
12
k
2
3
5
N
C
=
N
O
C
O
N
E
C
T
R266
100k
-
DN
P
R267
100k
-
DN
P
C
L
IP
S
IN
E
O
U
T
(D
E
F
A
U
L
T
)
D
N
P
:
D
O
N
O
T
P
O
P
U
L
A
T
E
O
P
T
IO
N
A
L
E
X
T
R
E
F
0
5965-
016
Figure 63. Evaluation Board Schematic, DUT, VREF, Clock Inputs, and Digital Output Interface
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