- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1986 > AD9259ABCPZRL7-50 (Analog Devices Inc)IC ADC 14BIT SRL 50MSPS 48LFCSP PDF資料下載
參數(shù)資料
| 型號： | AD9259ABCPZRL7-50 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 30/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT SRL 50MSPS 48LFCSP |
| 標準包裝： | 750 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 50M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉換器數(shù)目： | 4 |
| 功率耗散（最大）： | 409mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個單端，單極；4 個差分，單極 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當前第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
AD9259
Data Sheet
Rev. E | Page 36 of 52
DEFAULT OPERATION AND JUMPER SELECTION
SETTINGS
The following is a list of the default and optional settings or
modes allowed on the AD9259 Rev. A evaluation board.
POWER: Connect the switching power supply that is
provided in the evaluation kit between a rated 100 V ac to
240 V ac wall outlet at 47 Hz to 63 Hz and P503.
AIN: The evaluation board is set up for a transformer-
coupled analog input with an optimum 50 Ω impedance
match of 200 MHz of bandwidth (see Figure 61). For more
bandwidth response, the differential capacitor across the
analog inputs can be changed or removed. The common
mode of the analog inputs is developed from the center
tap of the transformer or AVDD_DUT/2.
0
AM
P
L
IT
UD
E
(
d
BF
S
)
FREQUENCY (MHz)
05
96
5-
0
88
0
–16
–14
–12
–10
–8
–6
–4
–2
50
100
150
200
250
300
350
400
450
500
–3dB CUTOFF = 200MHz
Figure 61. Evaluation Board Full-Power Bandwidth
VREF: VREF is set to 1.0 V by tying the SENSE pin to
ground, R237. This causes the ADC to operate in 2.0 V p-p
full-scale range. A separate external reference option using
the ADR510 is also included on the evaluation board.
Populate R231 and R235 and remove C214. Proper use of the
VREF options is noted in the Voltage Reference section.
RBIAS: RBIAS has a default setting of 10 kΩ (R201) to
ground and is used to set the ADC core bias current.
CLOCK: The default clock input circuitry is derived from a
simple transformer-coupled circuit using a high bandwidth
1:1 impedance ratio transformer (T201) that adds a very
low amount of jitter to the clock path. The clock input is
50 Ω terminated and ac-coupled to handle single-ended
sine wave types of inputs. The transformer converts the
single-ended input to a differential signal that is clipped
before entering the ADC clock inputs.
A differential LVPECL clock can also be used to clock the
ADC input using the AD9515 (U202). Populate R225 and
R227 with 0 Ω resistors and remove R217 and R218 to
disconnect the default clock path inputs. In addition, populate
C207 and C208 with a 0.1 μF capacitor and remove C210 and
C211 to disconnect the default clock path outputs. The
AD9515 has many pin-strappable options that are set to a
default mode of operation. Consult the AD9515 data sheet
for more information about these and other options.
In addition, an on-board oscillator is available on the OSC201
and can act as the primary clock source. The setup is quick
and involves installing R212 with a 0 Ω resistor and setting
the enable jumper (J205) to the on position. If the user wishes
to employ a different oscillator, two oscillator footprint options
are available (OSC201) to check the ADC performance.
PDWN: To enable the power-down feature, short J201 to
AVDD on the PDWN pin.
SCLK/DTP: To enable the digital test pattern on the digital
outputs of the ADC, use J204. If J204 is tied to AVDD during
device power-up, Test Pattern 10 0000 0000 0000 is enabled.
See the SCLK/DTP Pin section for details.
SDIO/ODM: To enable the low power, reduced signal option
(similar to the IEEE 1595.3 reduced range link LVDS output
standard), use J203. If J203 is tied to AVDD during device
power-up, it enables the LVDS outputs in a low power,
reduced signal option from the default ANSI-644 standard.
This option changes the signal swing from 350 mV p-p to
200 mV p-p, reducing the power of the DRVDD supply. See
the SDIO/ODM Pin section for more details.
CSB: To enable processing of the SPI information on the
SDIO and SCLK pins, tie J202 low in the always enable
mode. To ignore the SDIO and SCLK information, tie J202
to AVDD.
Non-SPI Mode: For users who wish to operate the DUT
without using SPI, remove Jumpers J202, J203, and J204.
This disconnects the CSB, SCLK/DTP, and SDIO/ODM
pins from the control bus, allowing the DUT to operate in its
simplest mode. Each of these pins has internal termination
and will float to its respective level.
D + x, D x: If an alternative data capture method to the setup
shown in Figure 60 is used, optional receiver terminations,
R206 to R211, can be installed next to the high speed back-
plane connector.
相關PDF資料 |
PDF描述 |
|---|---|
| AD9260ASZRL | IC ADC 16BIT 2.5MHZ 44MQFP |
| AD9262BCPZ-10 | IC ADC 16BIT 10MHZ 64LFCSP |
| AD9266BCPZRL7-20 | IC ADC 16BIT 20MSPS 32LFCSP |
| AD9269BCPZRL7-20 | IC ADC 16BIT 20MSPS DL 64LFCSP |
| AD9271BSVZ-40 | IC ADC OCT 12BIT 40MSPS 100-TQFP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9259BCPZ-50 | 制造商:Analog Devices 功能描述:ADC Quad Pipelined 50Msps 14-bit Serial (2-Wire)/LVDS 48-Pin LFCSP EP 制造商:Analog Devices 功能描述:14BIT 50 MSPS SERIAL LVDS ADC 制造商:Analog Devices 功能描述:14BIT ADC 50MSPS SMD LFCSP-48 |
| AD9259BCPZRL-50 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad, 14-bit, 50 MSPS Serial LVDS 1.8 V A/D Converter |
| AD9260 | 制造商:AD 制造商全稱:Analog Devices 功能描述:High-Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word Rate |
| AD9260AS | 制造商:Analog Devices 功能描述:ADC Single Pipelined 2.5Msps 16-bit Parallel 44-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:16-BIT HIGH SPEED OVERSAMPLED ADC - Bulk 制造商:Analog Devices 功能描述:Analog-Digital Converter IC Number of Bi |
| AD9260ASRL | 制造商:Analog Devices 功能描述:ADC Single Pipelined 2.5Msps 16-bit Parallel 44-Pin MQFP T/R 制造商:Rochester Electronics LLC 功能描述:16-BIT HIGH SPEED OVERSAMPLED ADC - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。