參數(shù)資料
型號： AD9269BCPZRL7-20
廠商： Analog Devices Inc
文件頁數(shù)： 19/40頁
文件大?。?/td> 0K
描述： IC ADC 16BIT 20MSPS DL 64LFCSP
標準包裝： 750
位數(shù)： 16
采樣率（每秒）： 20M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 102mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應商設備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個單端，單極；4 個單端，雙極；2 個差分，單極；2 個差分，雙極
AD9269
Rev. 0 | Page 26 of 40
BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
The AD9269 includes a built-in test feature that is designed to
enable verification of the integrity of each channel as well as to
facilitate board-level debugging. A built-in self-test (BIST) feature
that verifies the integrity of the digital datapath of the AD9269
is included. Various output test options are also provided to place
predictable values on the outputs of the AD9269.
BUILT-IN SELF-TEST (BIST)
The BIST is a thorough test of the digital portion of the selected
AD9269 signal path. Perform the BIST test after a reset to ensure
that the part is in a known state. During BIST, data from an internal
pseudorandom noise (PN) source is driven through the digital
datapath of both channels, starting at the ADC block output.
At the datapath output, CRC logic calculates a signature from
the data. The BIST sequence runs for 512 cycles and then stops.
When the sequence is complete, the BIST compares the signature
results with a predetermined value. If the signatures match, the
BIST sets Bit 0 in Register 0x24, signifying that the test passed.
If the BIST test failed, Bit 0 in Register 0x24 is cleared. The outputs
are connected during this test, so the PN sequence can be observed
as it runs. Writing the value 0x05 to Register 0x0E runs the BIST.
This enables Bit 0 (BIST enable) in Register 0x0E and resets the PN
sequence generator, Bit 2 (BIST init) in Register 0x0E. At the
completion of the BIST, Bit 0 in Register 0x24 is automatically
cleared. The PN sequence can be continued from its last value
by writing a 0 in Bit 2 in Register 0x0E. However, if the PN
sequence is not reset, the signature calculation does not equal the
predetermined value at the end of the test. At that point, the user
must rely on verifying the output data.
OUTPUT TEST MODES
The output test options are described in Table 17 at Address 0x0D.
When an output test mode is enabled, the analog section of the
ADC is disconnected from the digital back end blocks, and the
test pattern is run through the output formatting block. Some of
the test patterns are subject to output formatting, and some are
not. The PN generators from the PN sequence tests can be reset
by setting Bit 4 or Bit 5 in Register 0x0D. These tests can be per-
formed with or without an analog signal (if present, the analog
signal is ignored), but they do require an encode clock. For more
information, see the AN-877 Application Note, Interfacing to High
Speed ADCs via SPI.
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參數(shù)描述
AD9269BCPZRL7-40 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16 Bit 40 Msps low pwr dual ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風格: 封裝 / 箱體:
AD9269BCPZRL7-65 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16 Bit 65 Msps low pwr dual ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風格: 封裝 / 箱體:
AD9269BCPZRL7-80 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16 Bit 80 Msps low pwr dual ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風格: 封裝 / 箱體:
AD9271 制造商:AD 制造商全稱:Analog Devices 功能描述:Octal LNA/VGA/AAF/ADC and Crosspoint Switch
AD9271/PCBZ 制造商:Analog Devices 功能描述:EVAL BOARD - Bulk
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