參數(shù)資料
型號(hào)： AD9269BCPZRL7-20
廠商： Analog Devices Inc
文件頁數(shù)： 28/40頁
文件大?。?/td> 0K
描述： IC ADC 16BIT 20MSPS DL 64LFCSP
標(biāo)準(zhǔn)包裝： 750
位數(shù)： 16
采樣率（每秒）： 20M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 102mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個(gè)單端，單極；4 個(gè)單端，雙極；2 個(gè)差分，單極；2 個(gè)差分，雙極
AD9269
Rev. 0 | Page 34 of 40
Addr.
(Hex)
Register
Name
(MSB)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(LSB)
Bit 0
Default
Value
(Hex)
Comments
0x2A
Open
OR OE
(local)
0x01
Disable the OR pin
for the indexed
channel
0x2E
Output assign
Open
0 =
ADC A
1 =
ADC B
(local)
Ch A =
0x00
Ch B =
0x01
Assign an ADC
to an output
channel
Digital feature control
0x100
Sync control
(global)
Open
Clock
divider
next
sync
only
Clock
divider
sync
enable
Master
sync
enable
0x01
0x101
USR2
Enable
OEB
(Pin 47)
(local)
Open
Enable
GCLK
detect
Run
GCLK
Open
Disable
SDIO
pull-
down
0x88
Enables internal
oscillator for
clock rates of
<5 MHz
0x110
QEC Control 0
Open
Freeze DC
Freeze
phase
Freeze
gain
DC
enable
Phase
enable
Gain
enable
0x00
0x111
QEC Control 1
Open
Force
DC
Force
phase
Force
gain
0x00
0x112
QEC gain
bandwidth control
Open
KEXP_GAIN
0x02
0x113
QEC phase
bandwidth control
Open
KEXP_PHASE
0x02
0x114
QEC DC
bandwidth control
Open
KEXP_DC
0x02
0x116
QEC Initial Gain 0
Initial gain, Bits[7:0]
0x00
0x117
QEC Initial Gain 1
Open
Initial gain, Bits[14:8]
0x00
0x118
QEC Initial Phase 0
Initial phase, Bits[7:0]
0x00
0x119
QEC Initial Phase 1
Open
Initial phase, Bits[12:8]
0x00
0x11A
QEC Initial DC I 0
Initial DC I, Bits[7:0]
0x00
0x11B
QEC Initial DC I 1
Open
Initial DC I, Bits[13:8]
0x00
0x11C
QEC Initial DC Q 0
Initial DC Q, Bits[7:0]
0x00
0x11D
QEC Initial DC Q 1
Open
Initial DC Q, Bits[13:8]
0x00
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled in
Register 0x00 to Register 0xFF, see the AN-877 Application
Note, Interfacing to High Speed ADCs via SPI.
Sync Control (Register 0x100)
Bits[7:3]—Open
Bit 2—Clock Divider Next Sync Only
If the master sync enable bit (Address 0x100, Bit 0) and the
clock divider sync enable bit (Address 0x100, Bit 1) are high,
Bit 2 allows the clock divider to sync to the first sync pulse it
receives and to ignore the rest. The clock divider sync enable bit
(Address 0x100, Bit 1) resets after it syncs.
Bit 1—Clock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal is
enabled when Bit 1 and Bit 0 are high, and the device is operating
in continuous sync mode as long as Bit 2 of the sync control is low.
Bit 0—Master Sync Enable
Bit 0 must be high to enable any of the sync functions.
USR2 (Register 0x101)
Bit 7—Enable OEB (Pin 47)
Normally set high, this bit allows Pin 47 to function as the output
enable. If this bit is set low, it disables Pin 47.
Bits [6:4]—Open
Bit 3—Enable GCLK Detect
Normally set high, this bit enables a circuit that detects encode
rates below ~5 MSPS. When a low encode rate is detected, an
internal oscillator, GCLK, is enabled to ensure the proper operation
of several circuits. If this bit is set low, the detector is disabled.
Bit 2—Run GCLK
This bit enables the GCLK oscillator. For some applications
with encode rates below 10 MSPS, it may be preferable to set
this bit high to supersede the GCLK detector.
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