參數(shù)資料
型號： AD9269BCPZRL7-20
廠商： Analog Devices Inc
文件頁數(shù)： 2/40頁
文件大?。?/td> 0K
描述： IC ADC 16BIT 20MSPS DL 64LFCSP
標(biāo)準(zhǔn)包裝： 750
位數(shù)： 16
采樣率（每秒）： 20M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 102mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個單端，單極；4 個單端，雙極；2 個差分，單極；2 個差分，雙極
AD9269
Rev. 0 | Page 10 of 40
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
Rating
AVDD to AGND
0.3 V to +2.0 V
DRVDD to AGND
0.3 V to +3.9 V
VIN+A, VIN+B, VINA, VINB to AGND
0.3 V to AVDD + 0.2 V
CLK+, CLK to AGND
0.3 V to AVDD + 0.2 V
SYNC to AGND
0.3 V to DRVDD + 0.3 V
VREF to AGND
0.3 V to AVDD + 0.2 V
SENSE to AGND
0.3 V to AVDD + 0.2 V
VCM to AGND
0.3 V to AVDD + 0.2 V
RBIAS to AGND
0.3 V to AVDD + 0.2 V
CSB to AGND
0.3 V to DRVDD + 0.3 V
SCLK/DFS to AGND
0.3 V to DRVDD + 0.3 V
SDIO/DCS to AGND
0.3 V to DRVDD + 0.3 V
OEB to AGND
0.3 V to DRVDD + 0.3 V
PDWN to AGND
0.3 V to DRVDD + 0.3 V
D0x through D15x to AGND
0.3 V to DRVDD + 0.3 V
DCOx to AGND
0.3 V to DRVDD + 0.3 V
Operating Temperature Range (Ambient)
40°C to +85°C
Maximum Junction Temperature Under Bias
150°C
Storage Temperature Range (Ambient)
65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
The exposed paddle is the only ground connection for the chip.
The exposed paddle must be soldered to the AGND plane of the
user’s PCB. Soldering the exposed paddle to the user’s board
also increases the reliability of the solder joints and maximizes
the thermal capability of the package.
Table 7. Thermal Resistance
Package Type
Airflow
Velocity
(m/sec)
Unit
64-Lead LFCSP
9 mm × 9 mm
(CP-64-4)
0
23
2.0
°C/W
1.0
20
12
°C/W
2.5
18
°C/W
1 Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.
2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3 Per MIL-Std 883, Method 1012.1.
4 Per JEDEC JESD51-8 (still air).
Typical θJA is specified for a 4-layer PCB with a solid ground
plane. As shown in Table 7, airflow improves heat dissipation,
which reduces θJA. In addition, metal in direct contact with the
package leads from metal traces, through holes, ground, and
power planes, reduces the θJA.
ESD CAUTION
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