參數(shù)資料
型號(hào)： AD9269BCPZRL7-20
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 15/40頁(yè)
文件大?。?/td> 0K
描述： IC ADC 16BIT 20MSPS DL 64LFCSP
標(biāo)準(zhǔn)包裝： 750
位數(shù)： 16
采樣率（每秒）： 20M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 102mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 4 個(gè)單端，單極；4 個(gè)單端，雙極；2 個(gè)差分，單極；2 個(gè)差分，雙極
AD9269
Rev. 0 | Page 22 of 40
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or to improve thermal drift
characteristics. Figure 47 shows the typical drift characteristics
of the internal reference in 1.0 V mode.
4
3
2
1
0
–1
–2
–3
–4
–5
–6
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
V
RE
F
E
RRO
R
(
m
V
)
VREF ERROR (mV)
0
85
38
-05
2
Figure 47. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7.5 kΩ load (see Figure 32). The internal buffer generates the
positive and negative full-scale references for the ADC core.
Therefore, the external reference must be limited to a maximum
of 1.0 V.
CLOCK INPUT CONSIDERATIONS
For optimum performance, clock the AD9269 sample clock
inputs, CLK+ and CLK, with a differential signal. The signal
is typically ac-coupled into the CLK+ and CLK pins via a
transformer or capacitors. These pins are biased internally
(see Figure 48) and require no external bias.
0.9V
AVDD
2pF
CLK–
CLK+
08
53
8-
01
6
Figure 48. Equivalent Clock Input Circuit
Clock Input Options
The AD9269 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter
is of the most concern, as described in the Jitter Considerations
section.
Figure 49 and Figure 50 show two preferred methods for clock-
ing the AD9269 (at rates up to 6× the specified sample rate when
using the internal clock divider function). A low jitter clock source
is converted from a single-ended signal to a differential signal
using either an RF balun or an RF transformer.
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 480 MHz, and the RF transformer is recom-
mended for clock frequencies from 10 MHz to 200 MHz. The
back-to-back Schottky diodes across the transformer/balun
secondary limit clock excursions into the AD9269 to approxi-
mately 0.8 V p-p differential.
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9269 while pre-
serving the fast rise and fall times of the signal that are critical to
a low jitter performance.
0.1F
1nF
CLOCK
INPUT
1nF
50
CLK–
CLK+
SCHOTTKY
DIODES:
HSMS2822
ADC
08
53
8-
01
8
Figure 49. Balun-Coupled Differential Clock (Up to 480 MHz)
0.1F
SCHOTTKY
DIODES:
HSMS2822
CLOCK
INPUT
50
100
CLK–
CLK+
ADC
Mini-Circuits
ADT1-1WT, 1:1 Z
XFMR
08
53
8-
0
17
Figure 50. Transformer-Coupled Differential Clock (Up to 200 MHz)
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AD9269BCPZRL7-40 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16 Bit 40 Msps low pwr dual ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類(lèi)型: 信噪比: 接口類(lèi)型: 工作電源電壓: 最大工作溫度: 安裝風(fēng)格: 封裝 / 箱體:
AD9269BCPZRL7-65 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16 Bit 65 Msps low pwr dual ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類(lèi)型: 信噪比: 接口類(lèi)型: 工作電源電壓: 最大工作溫度: 安裝風(fēng)格: 封裝 / 箱體:
AD9269BCPZRL7-80 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16 Bit 80 Msps low pwr dual ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類(lèi)型: 信噪比: 接口類(lèi)型: 工作電源電壓: 最大工作溫度: 安裝風(fēng)格: 封裝 / 箱體:
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