參數(shù)資料
型號(hào): AD9269BCPZRL7-20
廠商: Analog Devices Inc
文件頁(yè)數(shù): 39/40頁(yè)
文件大?。?/td> 0K
描述: IC ADC 16BIT 20MSPS DL 64LFCSP
標(biāo)準(zhǔn)包裝: 750
位數(shù): 16
采樣率(每秒): 20M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 102mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 4 個(gè)單端,單極;4 個(gè)單端,雙極;2 個(gè)差分,單極;2 個(gè)差分,雙極
AD9269
Rev. 0 | Page 8 of 40
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = 1.0 dBFS, DCS disabled,
unless otherwise noted.
Table 4.
Parameter
Temp
AD9269-20/AD9269-40
AD9269-65
AD9269-80
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
CLOCK INPUT PARAMETERS
Input Clock Rate
Full
480
MHz
Conversion Rate1
Full
3
20/40
3
65
3
80
MSPS
CLK Period—Divide-by-1 Mode (tCLK)
Full
50/25
15.38
12.5
ns
CLK Pulse Width High (tCH)
25.0/12.5
7.69
6.25
ns
Aperture Delay (tA)
Full
1.0
ns
Aperture Uncertainty (Jitter, tJ)
Full
0.1
ps rms
DATA OUTPUT PARAMETERS
Data Propagation Delay (tPD)
Full
3
ns
DCO Propagation Delay (tDCO)
Full
3
ns
DCO to Data Skew (tSKEW)
Full
0.1
ns
Pipeline Delay (Latency)
Full
9
Cycles
With QEC Active
Full
11
Cycles
Wake-Up Time2
Full
350
μs
Standby
Full
600/400
300
260
ns
OUT-OF-RANGE RECOVERY TIME
Full
2
Cycles
1 Conversion rate is the clock rate after the CLK divider.
2 Wake-up time is dependent on the value of the decoupling capacitors.
tPD
tSKEW
tCH
tDCO
tCLK
N – 9
N – 1
N + 1
N + 2
N + 3
N + 5
N + 4
N
N – 8
N – 7
N – 6
N – 5
VIN
CLK+
CLK–
CH A/CH B DATA
DCOA/DCOB
tA
0
853
8-
002
Figure 2. CMOS Output Data Timing
tPD
tSKEW
tCH
tDCO
tCLK
CH A
N – 9
CH B
N – 9
CH A
N – 8
CH B
N – 8
CH A
N – 7
CH B
N – 7
CH A
N – 6
CH B
N – 6
CH A
N – 5
N – 1
N + 1
N + 2
N + 3
N + 5
N + 4
N
VIN
CLK+
CLK–
CH A/CH B DATA
DCOA/DCOB
tA
0
853
8-
003
Figure 3. CMOS Interleaved Output Timing
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