參數(shù)資料
型號(hào): AD9517-4A/PCBZ
廠商: Analog Devices Inc
文件頁數(shù): 18/80頁
文件大小: 0K
描述: BOARD EVALUATION FOR AD9517-4A
設(shè)計(jì)資源: High Performance, Dual Channel IF Sampling Receiver (CN0140)
AD9517 Eval Brd Schematics
AD9517 Gerber Files
AD9517-4 BOM
標(biāo)準(zhǔn)包裝: 1
主要目的: 計(jì)時(shí),時(shí)鐘發(fā)生器
嵌入式:
已用 IC / 零件: AD9517-4A
主要屬性: 2 輸入,12 輸出,1.6GHz VCO
次要屬性: CMOS,LVPECL 和 LVDS 兼容
已供物品:
Data Sheet
AD9517-4
Rev. E | Page 25 of 80
–100
–110
–120
–130
–140
–150
–160
10
100M
10M
1M
100k
10k
1k
100
PH
A
SE
N
O
ISE
(d
B
c
/H
z)
FREQUENCY (Hz)
06428-
132
Figure 37. Phase Noise (Additive) CMOS at 250 MHz, Divide-by-4
–120
–160
–150
–140
–130
1k
100M
10M
1M
100k
10k
PH
A
SE
N
O
ISE
(d
B
c
/H
z)
FREQUENCY (Hz)
06428-
208
Figure 38. Phase Noise (Absolute) Clock Generation; Internal VCO at
1.475 GHz; PFD = 15.36 MHz; LBW = 135 kHz; LVPECL Output = 122.88 MHz
–90
–100
–110
–120
–130
–140
–150
–160
1k
100M
10M
1M
100k
10k
PH
A
SE
N
O
ISE
(d
B
c
/H
z)
FREQUENCY (Hz)
06428-
209
Figure 39. Phase Noise (Absolute) Clock Cleanup; Internal VCO at 1.556 GHz;
PFD = 19.44 MHz; LBW = 12.8 kHz; LVPECL Output = 155.52 MHz
–120
–160
–150
–140
–130
1k
100M
10M
1M
100k
10k
PH
A
SE
N
O
ISE
(d
B
c
/H
z)
FREQUENCY (Hz)
06428-
140
Figure 40. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112) at
245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.76 MHz
1000
100
10
1
0.1
0.01
0.1
1
10
100
1000
IN
P
U
T
J
ITTE
R
A
M
P
LITU
D
E
(
U
Ip-
p)
JITTER FREQUENCY (kHz)
06427-
148
OC-48 OBJECTIVE MASK
AD9517
NOTE: 375UI MAX AT 10Hz OFFSET IS THE
MAXIMUM JITTER THAT CAN BE
GENERATED BY THE TEST EQUIPMENT.
FAILURE POINT IS GREATER THAN 375UI.
fOBJ
Figure 41. GR-253 Jitter Tolerance Plot
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