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參數(shù)資料
型號(hào): AD9517-4A/PCBZ
廠商: Analog Devices Inc
文件頁數(shù): 50/80頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR AD9517-4A
設(shè)計(jì)資源: High Performance, Dual Channel IF Sampling Receiver (CN0140)
AD9517 Eval Brd Schematics
AD9517 Gerber Files
AD9517-4 BOM
標(biāo)準(zhǔn)包裝: 1
主要目的: 計(jì)時(shí),時(shí)鐘發(fā)生器
嵌入式:
已用 IC / 零件: AD9517-4A
主要屬性: 2 輸入,12 輸出,1.6GHz VCO
次要屬性: CMOS,LVPECL 和 LVDS 兼容
已供物品:
AD9517-4
Data Sheet
Rev. E | Page 54 of 80
CS
SCLK
SDIO
tHIGH
tLOW
tCLK
tS
tDS
tDH
tC
BIT N
BIT N + 1
06
42
8-
0
43
Figure 69. Serial Control Port Timing—Write
Table 50. Serial Control Port Timing
Parameter
Description
tDS
Setup time between data and rising edge of SCLK
tDH
Hold time between data and rising edge of SCLK
tCLK
Period of the clock
tS
Setup time between CS falling edge and SCLK rising edge (start of communication cycle)
tC
Setup time between SCLK rising edge and CS rising edge (end of communication cycle)
tHIGH
Minimum period that SCLK should be in a logic high state
tLOW
Minimum period that SCLK should be in a logic low state
tDV
SCLK to valid SDIO and SDO (see Figure 67)
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