參數(shù)資料
型號(hào)： AD9517-4A/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 57/80頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD9517-4A
設(shè)計(jì)資源： High Performance, Dual Channel IF Sampling Receiver (CN0140)
AD9517 Eval Brd Schematics
AD9517 Gerber Files
AD9517-4 BOM
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9517-4A
主要屬性： 2 輸入，12 輸出，1.6GHz VCO
次要屬性： CMOS，LVPECL 和 LVDS 兼容
已供物品： 板
AD9517-4
Data Sheet
Rev. E | Page 60 of 80
Table 54. PLL
Reg.
Addr.
(Hex)
Bits
Name
Description
0x010
7
PFD polarity
Sets the PFD polarity. Negative polarity is for use (if needed) with external VCO/VCXO only. The on-chip VCO requires
positive polarity; Bit 7 = 0b.
0: positive; higher control voltage produces higher frequency (default).
1: negative; higher control voltage produces lower frequency.
[6:4]
CP current
Charge pump current (with CPRSET = 5.1 k).
6
5
4
ICP (mA)
0
0.6
0
1
1.2
0
1
0
1.8
0
1
2.4
1
0
3.0
1
0
1
3.6
1
0
4.2
1
4.8 (default)
[3:2]
CP mode
Charge pump operating mode.
3
2
Charge Pump Mode
0
High impedance state.
0
1
Force source current (pump up).
1
0
Force sink current (pump down).
1
Normal operation (default).
[1:0]
PLL power-down
PLL operating mode.
1
0
Mode
0
Normal operation.
0
1
Asynchronous power-down (default).
1
0
Normal operation.
1
Synchronous power-down.
0x011
[7:0]
14-bit R divider,
Bits[7:0] (LSB)
R divider LSBs—lower eight bits (default = 0x01).
0x012
[5:0]
14-bit R divider,
Bits[13:8] (MSB)
R divider MSBs—upper six bits (default = 0x00).
0x013
[5:0]
6-bit A counter
A counter (part of N divider) (default = 0x00).
0x014
[7:0]
13-bit B counter,
Bits[7:0] (LSB)
B counter (part of N divider)—lower eight bits (default = 0x03).
0x015
[4:0]
13-bit B counter,
Bits[12:8] (MSB)
B counter (part of N divider)—upper five bits (default = 0x00).
0x016
7
Set CP pin to VCP/2
Sets the CP pin to one-half of the VCP supply voltage.
0: CP normal operation (default).
1: CP pin set to VCP/2.
6
Reset R counter
Resets R counter (R divider).
0: normal (default).
1: holds the R counter in reset.
5
Reset A, B counters
Resets A and B counters (part of N divider).
0: normal (default).
1: holds the A and B counters in reset.
4
Reset all counters
Resets R, A, and B counters.
0: normal (default).
1: holds the R, A, and B counters in reset.
3
B counter
B counter bypass. This is valid only when operating the prescaler in FD mode.
bypass
0: normal (default).
1: B counter is set to divide-by-1. This allows the prescaler setting to determine the divide for the N divider.
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